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Item: (req: (cip_tl_seq_item@23876) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }":[{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.107978856643470099904063092680119345347466202622310516154760333595453528544261","seed":107978856643470099904063092680119345347466202622310516154760333595453528544261,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":[").\n","UVM_INFO @  90215292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,47): Assertion MemTLResponseWithoutDebugIsError_A has failed":[{"name":"rv_dm_debug_disabled","qual_name":"0.rv_dm_debug_disabled.95916158829861706247867784791726714187503431780463788963010056443993092032657","seed":95916158829861706247867784791726714187503431780463788963010056443993092032657,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 160513730 ps: (rv_dm_enable_checker.sv:47) [ASSERT FAILED] MemTLResponseWithoutDebugIsError_A\n","UVM_INFO @ 160513730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*])":[{"name":"rv_dm_buffered_enable","qual_name":"0.rv_dm_buffered_enable.15498232175111898953033927955973815554728227198949823433894073445214665687740","seed":15498232175111898953033927955973815554728227198949823433894073445214665687740,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_buffered_enable/latest/run.log","log_context":["UVM_INFO @ 150654819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.16663601993692810806217881729292706654283107021187813928708085464036242597700","seed":16663601993692810806217881729292706654283107021187813928708085464036242597700,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"Job timed out after * minutes":[{"name":"rv_dm_stress_all","qual_name":"0.rv_dm_stress_all.52649886830376253449442333784645769516374997342610748103673709072232721191726","seed":52649886830376253449442333784645769516374997342610748103673709072232721191726,"line":null,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all/latest/run.log","log_context":[]}]}},"passed":40,"total":53,"percent":75.47169811320755}