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Item: (req: (cip_tl_seq_item@23867) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }":[{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.75152811575573412083374764478435536401816401597111324387902827443375150969317","seed":75152811575573412083374764478435536401816401597111324387902827443375150969317,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":[").\n","UVM_INFO @  76102616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.94650185248881151582045897693379977805935079021231583414203751389870878386262","seed":94650185248881151582045897693379977805935079021231583414203751389870878386262,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":42,"total":53,"percent":79.24528301886792}