{"block":{"name":"clkmgr","variant":null,"commit":"119f86a224419c5317ef7158da5bd89a3631f772","commit_short":"119f86a","dirty":true,"branch":"master","url":"https://github.com/lowRISC/opentitan/tree/119f86a224419c5317ef7158da5bd89a3631f772","revision_info":"GitHub Revision: [`119f86a`](https://github.com/lowrisc/opentitan/tree/119f86a224419c5317ef7158da5bd89a3631f772)"},"tool":{"name":"vcs","version":"unknown"},"timestamp":"2026-09-03T16:40:21Z","build_seed":null,"testplan_ref":"https://opentitan.org/book/hw/top_darjeeling/ip_autogen/clkmgr/data/clkmgr_testplan.html","stages":{"V1":{"testpoints":{"smoke":{"tests":{"clkmgr_smoke":{"max_time":2.28,"sim_time":88.929836,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_hw_reset":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.55,"sim_time":46.90912,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_rw":{"tests":{"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_bit_bash":{"tests":{"clkmgr_csr_bit_bash":{"max_time":5.5,"sim_time":447.66606800000005,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"csr_aliasing":{"tests":{"clkmgr_csr_aliasing":{"max_time":1.09,"sim_time":15.137186999999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"csr_mem_rw_with_rand_reset":{"tests":{"clkmgr_csr_mem_rw_with_rand_reset":{"max_time":1.72,"sim_time":22.363761999999998,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"regwen_csr_and_corresponding_lockable_csr":{"tests":{"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":1.09,"sim_time":15.137186999999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":2,"percent":50.0}},"passed":3,"total":6,"percent":50.0},"V2":{"testpoints":{"peri_enables":{"tests":{"clkmgr_peri":{"max_time":1.4,"sim_time":37.523995,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"trans_enables":{"tests":{"clkmgr_trans":{"max_time":0.97,"sim_time":17.367248,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"clk_status":{"tests":{"clkmgr_clk_status":{"max_time":1.27,"sim_time":26.341574,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"jitter":{"tests":{"clkmgr_smoke":{"max_time":2.28,"sim_time":88.929836,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"frequency":{"tests":{"clkmgr_frequency":{"max_time":1.27,"sim_time":29.459631,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_timeout":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.88,"sim_time":6.980125,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"frequency_overflow":{"tests":{"clkmgr_frequency":{"max_time":1.27,"sim_time":29.459631,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all":{"tests":{"clkmgr_stress_all":{"max_time":1.14,"sim_time":15.806213,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"alert_test":{"tests":{"clkmgr_alert_test":{"max_time":1.23,"sim_time":21.389205,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_oob_addr_access":{"tests":{"clkmgr_tl_errors":{"max_time":2.38,"sim_time":29.402158,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_illegal_access":{"tests":{"clkmgr_tl_errors":{"max_time":2.38,"sim_time":29.402158,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"tl_d_outstanding_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.55,"sim_time":46.90912,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":1.09,"sim_time":15.137186999999999,"passed":1,"total":1,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":1.0,"sim_time":12.293316,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":4,"percent":50.0},"tl_d_partial_access":{"tests":{"clkmgr_csr_hw_reset":{"max_time":1.55,"sim_time":46.90912,"passed":1,"total":1,"percent":100.0},"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0},"clkmgr_csr_aliasing":{"max_time":1.09,"sim_time":15.137186999999999,"passed":1,"total":1,"percent":100.0},"clkmgr_same_csr_outstanding":{"max_time":1.0,"sim_time":12.293316,"passed":0,"total":1,"percent":0.0}},"passed":2,"total":4,"percent":50.0}},"passed":8,"total":13,"percent":61.53846153846154},"V2S":{"testpoints":{"tl_intg_err":{"tests":{"clkmgr_sec_cm":{"max_time":2.1,"sim_time":125.63130100000001,"passed":0,"total":1,"percent":0.0},"clkmgr_tl_intg_err":{"max_time":1.0,"sim_time":7.536868999999999,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0},"shadow_reg_update_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.85,"sim_time":83.823462,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_read_clear_staged_value":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.85,"sim_time":83.823462,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_storage_error":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.85,"sim_time":83.823462,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadowed_reset_glitch":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.85,"sim_time":83.823462,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"shadow_reg_update_error_with_csr_rw":{"tests":{"clkmgr_shadow_reg_errors_with_csr_rw":{"max_time":2.15,"sim_time":105.871541,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_bus_integrity":{"tests":{"clkmgr_tl_intg_err":{"max_time":1.0,"sim_time":7.536868999999999,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_clk_bkgn_chk":{"tests":{"clkmgr_frequency":{"max_time":1.27,"sim_time":29.459631,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_timeout_clk_bkgn_chk":{"tests":{"clkmgr_frequency_timeout":{"max_time":0.88,"sim_time":6.980125,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_config_shadow":{"tests":{"clkmgr_shadow_reg_errors":{"max_time":1.85,"sim_time":83.823462,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_idle_intersig_mubi":{"tests":{"clkmgr_idle_intersig_mubi":{"max_time":2.4,"sim_time":97.51633199999999,"passed":1,"total":1,"percent":100.0}},"passed":1,"total":1,"percent":100.0},"sec_cm_jitter_config_mubi":{"tests":{"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_idle_ctr_redun":{"tests":{"clkmgr_sec_cm":{"max_time":2.1,"sim_time":125.63130100000001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_meas_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"sec_cm_clk_ctrl_config_regwen":{"tests":{"clkmgr_csr_rw":{"max_time":0.94,"sim_time":4.057777,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"prim_count_check":{"tests":{"clkmgr_sec_cm":{"max_time":2.1,"sim_time":125.63130100000001,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":2,"total":8,"percent":25.0},"V3":{"testpoints":{"regwen":{"tests":{"clkmgr_regwen":{"max_time":0.96,"sim_time":3.298725,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0},"stress_all_with_rand_reset":{"tests":{"clkmgr_stress_all_with_rand_reset":{"max_time":2.0,"sim_time":47.442330999999996,"passed":0,"total":1,"percent":0.0}},"passed":0,"total":1,"percent":0.0}},"passed":0,"total":2,"percent":0.0}},"coverage":{"code":{"block":null,"line_statement":81.46,"branch":86.53,"condition_expression":76.96,"toggle":95.94,"fsm":0.0},"assertion":89.05,"functional":59.35},"cov_report_page":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/cov_report/dashboard.html","vplan_report_page":null,"vplan_coverage":null,"failed_jobs":{"buckets":{"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency","qual_name":"0.clkmgr_frequency.51264771470938851206895842881813259982626080969245306789620885724909738819297","seed":51264771470938851206895842881813259982626080969245306789620885724909738819297,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest/run.log","log_context":["UVM_INFO @  29459631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all","qual_name":"0.clkmgr_stress_all.89158858598214118851397410458750461660913152936751972893313547862674843509880","seed":89158858598214118851397410458750461660913152936751972893313547862674843509880,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all/latest/run.log","log_context":["UVM_INFO @  15806213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*":[{"name":"clkmgr_frequency_timeout","qual_name":"0.clkmgr_frequency_timeout.31251899233144892693400394254154801445082979660674732584935021765078894442933","seed":31251899233144892693400394254154801445082979660674732584935021765078894442933,"line":84,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log","log_context":["UVM_INFO @   6980125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_stress_all_with_rand_reset","qual_name":"0.clkmgr_stress_all_with_rand_reset.102455349062501205518125188584289205525954077824073220028807930791723384367851","seed":102455349062501205518125188584289205525954077824073220028807930791723384367851,"line":177,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  47442331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en":[{"name":"clkmgr_regwen","qual_name":"0.clkmgr_regwen.59391687406551245784634219725417304398013052006174598194374390874443710173183","seed":59391687406551245784634219725417304398013052006174598194374390874443710173183,"line":80,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest/run.log","log_context":["UVM_INFO @   3298725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *":[{"name":"clkmgr_shadow_reg_errors_with_csr_rw","qual_name":"0.clkmgr_shadow_reg_errors_with_csr_rw.48234227114571877542032259505527946163216858557376612361514400016229991482630","seed":48234227114571877542032259505527946163216858557376612361514400016229991482630,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest/run.log","log_context":["UVM_INFO @ 105871541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_rw","qual_name":"0.clkmgr_csr_rw.106725152910452581625893321569554528772635852770486111290447138323931243949249","seed":106725152910452581625893321569554528772635852770486111290447138323931243949249,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest/run.log","log_context":["UVM_INFO @   4057777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"clkmgr_csr_mem_rw_with_rand_reset","qual_name":"0.clkmgr_csr_mem_rw_with_rand_reset.29669682415970583651822535338150391249731316978361153752799050697280242550815","seed":29669682415970583651822535338150391249731316978361153752799050697280242550815,"line":82,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  22363762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.":[{"name":"clkmgr_sec_cm","qual_name":"0.clkmgr_sec_cm.70812474204782390363082409382269969980165068445094819511611046756900120719943","seed":70812474204782390363082409382269969980165068445094819511611046756900120719943,"line":200,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest/run.log","log_context":["UVM_INFO @ 125631301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *":[{"name":"clkmgr_tl_intg_err","qual_name":"0.clkmgr_tl_intg_err.28989841988099663199336312242486071761669092622633366219760867596871583770470","seed":28989841988099663199336312242486071761669092622633366219760867596871583770470,"line":102,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest/run.log","log_context":["UVM_INFO @   7536869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *":[{"name":"clkmgr_csr_bit_bash","qual_name":"0.clkmgr_csr_bit_bash.893135008674405366137320081088326223128665816886261457394522632437705382186","seed":893135008674405366137320081088326223128665816886261457394522632437705382186,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest/run.log","log_context":["UVM_INFO @ 447666068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch":[{"name":"clkmgr_same_csr_outstanding","qual_name":"0.clkmgr_same_csr_outstanding.55858285046718045309815804180311214392468166906862573693655725941390395411766","seed":55858285046718045309815804180311214392468166906862573693655725941390395411766,"line":81,"log_path":"/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest/run.log","log_context":["UVM_INFO @  12293316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":10,"total":22,"percent":45.45454545454545}