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(/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 283135861 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed \n","xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 283135861 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed \n","UVM_ERROR @ 283135861 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid\n"]}],"UVM_FATAL (aes_base_vseq.sv:334) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG":[{"name":"aes_stress_all_with_rand_reset","qual_name":"0.aes_stress_all_with_rand_reset.34511009253802328055596727820807392015305853574620597649395598029459184695438","seed":34511009253802328055596727820807392015305853574620597649395598029459184695438,"line":572,"log_path":"/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 15331043061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":30,"total":35,"percent":85.71428571428571}