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Item: (req: (cip_tl_seq_item@23900) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }":[{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.31850081374928540324971423779254163695668328436862822229236481946549732006906","seed":31850081374928540324971423779254163695668328436862822229236481946549732006906,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":[").\n","UVM_INFO @  44756684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed":[{"name":"rv_dm_debug_disabled","qual_name":"0.rv_dm_debug_disabled.80045517263847553710109257447476141162316372144033804112665391202067460965215","seed":80045517263847553710109257447476141162316372144033804112665391202067460965215,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest/run.log","log_context":["UVM_ERROR @  80594499 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)  \n","UVM_INFO @  80594499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.6185845843920430583154050041334346189332495236730998465521213856835058488630","seed":6185845843920430583154050041334346189332495236730998465521213856835058488630,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.109711839493685203798470968447828594466998912739691719746521455210081299387328","seed":109711839493685203798470968447828594466998912739691719746521455210081299387328,"line":101,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 953597713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":41,"total":53,"percent":77.35849056603773}