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Item: (req: (cip_tl_seq_item@23890) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }":[{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.43385133366053033116398753343326118686503830083156583344782458407226619227928","seed":43385133366053033116398753343326118686503830083156583344782458407226619227928,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":[").\n","UVM_INFO @  71691744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed":[{"name":"rv_dm_debug_disabled","qual_name":"0.rv_dm_debug_disabled.25138080297227659886332784463547016779536864298491968080657500065825084776458","seed":25138080297227659886332784463547016779536864298491968080657500065825084776458,"line":91,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest/run.log","log_context":["UVM_ERROR @  45494009 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)  \n","UVM_INFO @  45494009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.15795168762263726706597826156658966444857365695539617319965232345448516003962","seed":15795168762263726706597826156658966444857365695539617319965232345448516003962,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":41,"total":53,"percent":77.35849056603773}