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otp_ctrl_core_reg_block.intr_state":[{"name":"otp_ctrl_dai_lock","qual_name":"0.otp_ctrl_dai_lock.52171165998616651476913889512241055269703225439822029485479469207855362573220","seed":52171165998616651476913889512241055269703225439822029485479469207855362573220,"line":11066,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log","log_context":["UVM_INFO @ 924308523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_parallel_key_req","qual_name":"0.otp_ctrl_parallel_key_req.55001523732947225673929277591664555239832991252847150544667896719779633196286","seed":55001523732947225673929277591664555239832991252847150544667896719779633196286,"line":24939,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest/run.log","log_context":["UVM_INFO @ 2453973018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error":[{"name":"otp_ctrl_macro_errs","qual_name":"0.otp_ctrl_macro_errs.19625557718732842118098691349588927697425351335001015877598556194888810769269","seed":19625557718732842118098691349588927697425351335001015877598556194888810769269,"line":995,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest/run.log","log_context":["UVM_INFO @ 423214896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]},{"name":"otp_ctrl_stress_all","qual_name":"0.otp_ctrl_stress_all.103103256956299102759092255620046318614235846208811535065095884534248425654908","seed":103103256956299102759092255620046318614235846208811535065095884534248425654908,"line":22996,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest/run.log","log_context":["UVM_INFO @ 2773787597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr c* rdata* readout mismatch":[{"name":"otp_ctrl_stress_all_with_rand_reset","qual_name":"0.otp_ctrl_stress_all_with_rand_reset.68820353731274867611866990698667922767686214866114299572960397836554827201931","seed":68820353731274867611866990698667922767686214866114299572960397836554827201931,"line":101,"log_path":"/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @ 6655508955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":21,"total":30,"percent":70.0}