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Item: (req: (cip_tl_seq_item@24934) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }":[{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.59630141177789392397154457049368017394125080157672234461168115796518878884044","seed":59630141177789392397154457049368017394125080157672234461168115796518878884044,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":[").\n","UVM_INFO @ 109994599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.5538084853420803206058245313105328092247871238364483840277899367622950057238","seed":5538084853420803206058245313105328092247871238364483840277899367622950057238,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_stress_all_vseq] m_mode_sequencer not configured.":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.44799060613296031262830454847904955611096169117583667260037819904684184629829","seed":44799060613296031262830454847904955611096169117583667260037819904684184629829,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  61306645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_common_vseq] m_mode_sequencer not configured.":[{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"0.rv_dm_csr_mem_rw_with_rand_reset.102680924083572931503032200546162381896431756199884750363329372622299518422310","seed":102680924083572931503032200546162381896431756199884750363329372622299518422310,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  93294262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":39,"total":53,"percent":73.58490566037736}