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Item: (req: (cip_tl_seq_item@24941) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }":[{"name":"rv_dm_rom_read_access","qual_name":"0.rv_dm_rom_read_access.62292728071903226724969801117028784681071227771920279653347908121460611086126","seed":62292728071903226724969801117028784681071227771920279653347908121460611086126,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_rom_read_access/latest/run.log","log_context":[").\n","UVM_INFO @  91073201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"xmsim: *E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_*/rv_dm_enable_checker.sv,47): Assertion MemTLResponseWithoutDebugIsError_A has failed":[{"name":"rv_dm_debug_disabled","qual_name":"0.rv_dm_debug_disabled.76816910168180387889911107749972059694885534739505510375366244756031470830560","seed":76816910168180387889911107749972059694885534739505510375366244756031470830560,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_debug_disabled/latest/run.log","log_context":["UVM_ERROR @ 104908845 ps: (rv_dm_enable_checker.sv:47) [ASSERT FAILED] MemTLResponseWithoutDebugIsError_A\n","UVM_INFO @ 104908845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n"]}],"UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue":[{"name":"rv_dm_scanmode","qual_name":"0.rv_dm_scanmode.78254592785807048321952815746368187898995120467453471907574584292913126733817","seed":78254592785807048321952815746368187898995120467453471907574584292913126733817,"line":87,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_scanmode/latest/run.log","log_context":["UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_stress_all_vseq] m_mode_sequencer not configured.":[{"name":"rv_dm_stress_all_with_rand_reset","qual_name":"0.rv_dm_stress_all_with_rand_reset.25619529101485758203282500184098343373016311811441200840874140829654426639738","seed":25619529101485758203282500184098343373016311811441200840874140829654426639738,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_stress_all_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  32243176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}],"UVM_FATAL (rv_dm_base_vseq.sv:139) virtual_sequencer [rv_dm_common_vseq] m_mode_sequencer not configured.":[{"name":"rv_dm_csr_mem_rw_with_rand_reset","qual_name":"0.rv_dm_csr_mem_rw_with_rand_reset.9722787386536182826524770659195777920424147353977951148234729753418196536493","seed":9722787386536182826524770659195777920424147353977951148234729753418196536493,"line":90,"log_path":"/nightly/current_run/scratch/master/rv_dm-sim-xcelium/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log","log_context":["UVM_INFO @  43994900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] \n","--- UVM Report catcher Summary ---\n","\n","\n"]}]}},"passed":38,"total":53,"percent":71.69811320754717}