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(uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *":[{"name":"uart_noise_filter","qual_name":"0.uart_noise_filter.27710916615159210676271392159091045421357792473932078046496921003102740671572","seed":27710916615159210676271392159091045421357792473932078046496921003102740671572,"line":86,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest/run.log","log_context":["UVM_ERROR @ 19289672002 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19294550785 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n","UVM_ERROR @ 19294550785 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0\n","UVM_ERROR @ 19295500279 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0\n"]}],"UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *":[{"name":"uart_stress_all","qual_name":"0.uart_stress_all.82947399899166696473230426750348464170927953319878511821191886954553911060230","seed":82947399899166696473230426750348464170927953319878511821191886954553911060230,"line":145,"log_path":"/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all/latest/run.log","log_context":["UVM_ERROR @ 217258975544 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n","UVM_ERROR @ 217258985961 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (19 [0x13] vs 239 [0xef]) reg name: uart_reg_block.rdata\n","UVM_ERROR @ 217448304519 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0\n","UVM_ERROR @ 217448325353 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty\n"]}]}},"passed":25,"total":27,"percent":92.5925925925926}