ADC_CTRL Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.900s	5.900ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.820s	983.793us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.690s	574.623us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	15.740s	26.650ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.260s	929.376us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.770s	602.040us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.690s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.260s	929.376us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.005m	326.507ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.038m	330.444ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.048m	324.779ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.031m	320.179ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.133m	343.342ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.382m	390.507ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.157m	339.714ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.910s	1.758ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.110s	4.575ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	12.600s	30.838ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	33.530s	78.778ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.563m	407.443ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.600s	545.456us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.570s	539.539us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.490s	799.250us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.490s	799.250us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.820s	983.793us	1	1	100.00
		adc_ctrl_csr_rw	1.690s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.260s	929.376us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.460s	1.894ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.820s	983.793us	1	1	100.00
		adc_ctrl_csr_rw	1.690s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.260s	929.376us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.460s	1.894ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.670s	4.428ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.960s	4.548ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.960s	4.548ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.300s	13.346ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.40	98.81	95.47	100.00	91.89	98.40	91.63	28.57

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.1
      Line 146, in log /nightly/runs/opentitan/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 1758090787 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 1758090787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---