70c7391684| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 0 | 1 | 0.00 | ||
| V1 | csr_hw_reset | csrng_csr_hw_reset | 0 | 1 | 0.00 | ||
| V1 | csr_rw | csrng_csr_rw | 0 | 1 | 0.00 | ||
| V1 | csr_bit_bash | csrng_csr_bit_bash | 0 | 1 | 0.00 | ||
| V1 | csr_aliasing | csrng_csr_aliasing | 0 | 1 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 0 | 1 | 0.00 | ||
| csrng_csr_aliasing | 0 | 1 | 0.00 | ||||
| V1 | TOTAL | 0 | 6 | 0.00 | |||
| V2 | interrupts | csrng_intr | 0 | 1 | 0.00 | ||
| V2 | alerts | csrng_alert | 0 | 1 | 0.00 | ||
| V2 | err | csrng_err | 0 | 1 | 0.00 | ||
| V2 | cmds | csrng_cmds | 0 | 1 | 0.00 | ||
| V2 | life cycle | csrng_cmds | 0 | 1 | 0.00 | ||
| V2 | stress_all | csrng_stress_all | 0 | 1 | 0.00 | ||
| V2 | intr_test | csrng_intr_test | 0 | 1 | 0.00 | ||
| V2 | alert_test | csrng_alert_test | 0 | 1 | 0.00 | ||
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_illegal_access | csrng_tl_errors | 0 | 1 | 0.00 | ||
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 0 | 1 | 0.00 | ||
| csrng_csr_rw | 0 | 1 | 0.00 | ||||
| csrng_csr_aliasing | 0 | 1 | 0.00 | ||||
| csrng_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 0 | 1 | 0.00 | ||
| csrng_csr_rw | 0 | 1 | 0.00 | ||||
| csrng_csr_aliasing | 0 | 1 | 0.00 | ||||
| csrng_same_csr_outstanding | 0 | 1 | 0.00 | ||||
| V2 | TOTAL | 0 | 9 | 0.00 | |||
| V2S | tl_intg_err | csrng_sec_cm | 0 | 1 | 0.00 | ||
| csrng_tl_intg_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_config_regwen | csrng_regwen | 0 | 1 | 0.00 | ||
| csrng_csr_rw | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_config_mubi | csrng_alert | 0 | 1 | 0.00 | ||
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 0 | 1 | 0.00 | ||
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 0 | 1 | 0.00 | ||
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 0 | 1 | 0.00 | ||
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 0 | 1 | 0.00 | ||
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| csrng_sec_cm | 0 | 1 | 0.00 | ||||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 0 | 1 | 0.00 | ||
| csrng_err | 0 | 1 | 0.00 | ||||
| V2S | TOTAL | 0 | 3 | 0.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 19 | 0.00 |
Job killed most likely because its dependent job failed. has 18 failures:
Test csrng_intr has 1 failures.
Test csrng_alert has 1 failures.
Test csrng_err has 1 failures.
Test csrng_regwen has 1 failures.
Test csrng_stress_all_with_rand_reset has 1 failures.
... and 12 more tests.
Job killed! has 3 failures:
Test csrng_smoke has 1 failures.
Test csrng_cmds has 1 failures.
Test csrng_stress_all has 1 failures.