GPIO Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.880s	271.204us	1	1	100.00
		gpio_smoke_no_pullup_pulldown	2.000s	271.204us	1	1	100.00
		gpio_smoke_en_cdc_prim	1.900s	277.621us	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.900s	277.621us	1	1	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	1.380s	56.535us	1	1	100.00
V1	csr_rw	gpio_csr_rw	1.460s	44.160us	1	1	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.670s	707.457us	1	1	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.720s	90.536us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.810s	127.078us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	1.460s	44.160us	1	1	100.00
		gpio_csr_aliasing	1.720s	90.536us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.560s	149.036us	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.650s	149.036us	1	1	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.450s	126.911us	1	1	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.740s	226.495us	1	1	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	2.370s	394.205us	1	1	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	2.610s	231.620us	1	1	100.00
V2	noise_filter_stress	gpio_filter_stress	10.720s	1.930ms	1	1	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	3.630s	937.043us	1	1	100.00
V2	full_random	gpio_full_random	1.590s	207.953us	1	1	100.00
V2	stress_all	gpio_stress_all	1.713m	44.361ms	1	1	100.00
V2	alert_test	gpio_alert_test	1.400s	45.785us	1	1	100.00
V2	intr_test	gpio_intr_test	1.400s	40.785us	1	1	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.650s	443.330us	1	1	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.650s	443.330us	1	1	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	1.460s	44.160us	1	1	100.00
		gpio_same_csr_outstanding	1.720s	99.077us	1	1	100.00
		gpio_csr_aliasing	1.720s	90.536us	1	1	100.00
		gpio_csr_hw_reset	1.380s	56.535us	1	1	100.00
V2	tl_d_partial_access	gpio_csr_rw	1.460s	44.160us	1	1	100.00
		gpio_same_csr_outstanding	1.720s	99.077us	1	1	100.00
		gpio_csr_aliasing	1.720s	90.536us	1	1	100.00
		gpio_csr_hw_reset	1.380s	56.535us	1	1	100.00
V2		TOTAL			14	14	100.00
V2S	tl_intg_err	gpio_tl_intg_err	2.840s	306.829us	1	1	100.00
		gpio_sec_cm	2.570s	254.579us	1	1	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	2.840s	306.829us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	20.480s	6.934ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	26	96.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	98.22	98.52	94.02	--	99.01	96.79	99.93

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.1
      Line 414, in log /nightly/runs/opentitan/scratch/master/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6934382196 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6934382196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---