HMAC Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.110s 1.189ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.750s 77.119us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.650s 65.036us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.580s 1.912ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.930s 728.374us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.610s 59.327us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.650s 65.036us 1 1 100.00
hmac_csr_aliasing 2.930s 728.374us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 33.930s 14.003ms 1 1 100.00
V2 back_pressure hmac_back_pressure 9.330s 945.834us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 6.373m 184.841ms 1 1 100.00
hmac_test_sha384_vectors 0 1 0.00
hmac_test_sha512_vectors 0 1 0.00
hmac_test_hmac256_vectors 27.100s 13.654ms 1 1 100.00
hmac_test_hmac384_vectors 36.550s 19.306ms 1 1 100.00
hmac_test_hmac512_vectors 47.430s 25.281ms 1 1 100.00
V2 burst_wr hmac_burst_wr 17.650s 7.354ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.508m 6.680ms 1 1 100.00
V2 error hmac_error 40.290s 17.177ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 18.710s 8.263ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.110s 1.189ms 1 1 100.00
hmac_long_msg 33.930s 14.003ms 1 1 100.00
hmac_back_pressure 9.330s 945.834us 1 1 100.00
hmac_datapath_stress 2.508m 6.680ms 1 1 100.00
hmac_burst_wr 17.650s 7.354ms 1 1 100.00
hmac_stress_all 8.009m 211.537ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.110s 1.189ms 1 1 100.00
hmac_long_msg 33.930s 14.003ms 1 1 100.00
hmac_back_pressure 9.330s 945.834us 1 1 100.00
hmac_datapath_stress 2.508m 6.680ms 1 1 100.00
hmac_wipe_secret 18.710s 8.263ms 1 1 100.00
hmac_test_sha256_vectors 6.373m 184.841ms 1 1 100.00
hmac_test_sha384_vectors 0 1 0.00
hmac_test_sha512_vectors 0 1 0.00
hmac_test_hmac256_vectors 27.100s 13.654ms 1 1 100.00
hmac_test_hmac384_vectors 36.550s 19.306ms 1 1 100.00
hmac_test_hmac512_vectors 47.430s 25.281ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.110s 1.189ms 1 1 100.00
hmac_long_msg 33.930s 14.003ms 1 1 100.00
hmac_back_pressure 9.330s 945.834us 1 1 100.00
hmac_datapath_stress 2.508m 6.680ms 1 1 100.00
hmac_burst_wr 17.650s 7.354ms 1 1 100.00
hmac_error 40.290s 17.177ms 1 1 100.00
hmac_wipe_secret 18.710s 8.263ms 1 1 100.00
hmac_test_sha256_vectors 6.373m 184.841ms 1 1 100.00
hmac_test_sha384_vectors 0 1 0.00
hmac_test_sha512_vectors 0 1 0.00
hmac_test_hmac256_vectors 27.100s 13.654ms 1 1 100.00
hmac_test_hmac384_vectors 36.550s 19.306ms 1 1 100.00
hmac_test_hmac512_vectors 47.430s 25.281ms 1 1 100.00
hmac_stress_all 8.009m 211.537ms 1 1 100.00
V2 stress_all hmac_stress_all 8.009m 211.537ms 1 1 100.00
V2 alert_test hmac_alert_test 1.620s 39.869us 1 1 100.00
V2 intr_test hmac_intr_test 1.570s 38.994us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.490s 370.455us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.490s 370.455us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.750s 77.119us 1 1 100.00
hmac_csr_rw 1.650s 65.036us 1 1 100.00
hmac_csr_aliasing 2.930s 728.374us 1 1 100.00
hmac_same_csr_outstanding 1.700s 208.870us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.750s 77.119us 1 1 100.00
hmac_csr_rw 1.650s 65.036us 1 1 100.00
hmac_csr_aliasing 2.930s 728.374us 1 1 100.00
hmac_same_csr_outstanding 1.700s 208.870us 1 1 100.00
V2 TOTAL 15 17 88.24
V2S tl_intg_err hmac_sec_cm 1.920s 140.244us 1 1 100.00
hmac_tl_intg_err 3.330s 371.413us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.330s 371.413us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.110s 1.189ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.760s 781.125us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 21.400s 7.677ms 1 1 100.00
V3 TOTAL 2 2 100.00
TOTAL 25 27 92.59

Failure Buckets