KEYMGR Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.370s	149.370us	1	1	100.00
V1	random	keymgr_random	2.800s	222.412us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.850s	64.202us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.840s	67.119us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.420s	1.795ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.180s	771.791us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.130s	98.411us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.840s	67.119us	1	1	100.00
		keymgr_csr_aliasing	5.180s	771.791us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.540s	105.328us	1	1	100.00
V2	sideload	keymgr_sideload	2.470s	157.495us	1	1	100.00
		keymgr_sideload_kmac	2.400s	145.536us	1	1	100.00
		keymgr_sideload_aes	2.380s	145.536us	1	1	100.00
		keymgr_sideload_otbn	2.370s	145.536us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.050s	89.661us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.700s	304.371us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.390s	260.495us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.250s	257.704us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.390s	265.704us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.350s	61.494us	1	1	100.00
V2	stress_all	keymgr_stress_all	25.630s	3.737ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.550s	29.869us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.590s	37.994us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.880s	249.620us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.880s	249.620us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.850s	64.202us	1	1	100.00
		keymgr_csr_rw	1.840s	67.119us	1	1	100.00
		keymgr_csr_aliasing	5.180s	771.791us	1	1	100.00
		keymgr_same_csr_outstanding	2.570s	185.537us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.850s	64.202us	1	1	100.00
		keymgr_csr_rw	1.840s	67.119us	1	1	100.00
		keymgr_csr_aliasing	5.180s	771.791us	1	1	100.00
		keymgr_same_csr_outstanding	2.570s	185.537us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
		keymgr_tl_intg_err	8.780s	441.747us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.530s	246.523us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.530s	246.523us	0	1	0.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.530s	246.523us	0	1	0.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.530s	246.523us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	8.070s	622.964us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.780s	441.747us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.530s	246.523us	0	1	0.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.540s	105.328us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.800s	222.412us	1	1	100.00
		keymgr_csr_rw	1.840s	67.119us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.800s	222.412us	1	1	100.00
		keymgr_csr_rw	1.840s	67.119us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.800s	222.412us	1	1	100.00
		keymgr_csr_rw	1.840s	67.119us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.700s	304.371us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.390s	265.704us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.390s	265.704us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.800s	222.412us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.480s	163.703us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.820s	219.203us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.700s	304.371us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.820s	219.203us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.820s	219.203us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.820s	219.203us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.110s	1.021ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.820s	219.203us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.430s	755.958us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.01	98.63	90.88	97.72	88.37	97.40	91.22	51.82

Failure Buckets

• UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 2 failures:

  • Test keymgr_shadow_reg_errors has 1 failures.

    • 0.keymgr_shadow_reg_errors.1
      Line 99, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest/run.log

        UVM_FATAL @ 246523377 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @ 246523377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.1
      Line 99, in log /nightly/runs/opentitan/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @ 622964243 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @ 622964243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---