70c7391684| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 38.400s | 11.283ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.550s | 59.077us | 1 | 1 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.570s | 64.827us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 7.360s | 2.020ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 4.100s | 797.041us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.130s | 171.078us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.570s | 64.827us | 1 | 1 | 100.00 |
| kmac_csr_aliasing | 4.100s | 797.041us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.490s | 36.952us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.900s | 103.036us | 1 | 1 | 100.00 |
| V1 | TOTAL | 8 | 8 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0 | 1 | 0.00 | ||
| V2 | burst_write | kmac_burst_write | 9.856m | 100.201ms | 1 | 1 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0 | 1 | 0.00 | ||
| kmac_test_vectors_sha3_256 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_sha3_384 | 0 | 1 | 0.00 | ||||
| kmac_test_vectors_sha3_512 | 10.858m | 128.993ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_128 | 2.311m | 39.877ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_shake_256 | 3.761m | 64.131ms | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac | 2.680s | 275.287us | 1 | 1 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 2.740s | 313.954us | 1 | 1 | 100.00 | ||
| V2 | sideload | kmac_sideload | 4.066m | 55.209ms | 1 | 1 | 100.00 |
| V2 | app | kmac_app | 3.267m | 47.547ms | 1 | 1 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 3.434m | 51.017ms | 1 | 1 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 3.282m | 51.099ms | 1 | 1 | 100.00 |
| V2 | error | kmac_error | 4.123m | 55.466ms | 1 | 1 | 100.00 |
| V2 | key_error | kmac_key_error | 5.270s | 3.738ms | 1 | 1 | 100.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.810s | 309.829us | 1 | 1 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 25.480s | 6.099ms | 1 | 1 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 22.510s | 5.518ms | 1 | 1 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 38.990s | 21.162ms | 1 | 1 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 4.240s | 395.705us | 1 | 1 | 100.00 |
| V2 | stress_all | kmac_stress_all | 0 | 1 | 0.00 | ||
| V2 | intr_test | kmac_intr_test | 1.500s | 33.452us | 1 | 1 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.510s | 41.660us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 2.310s | 228.412us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 2.310s | 228.412us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.550s | 59.077us | 1 | 1 | 100.00 |
| kmac_csr_rw | 1.570s | 64.827us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 4.100s | 797.041us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.960s | 167.411us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.550s | 59.077us | 1 | 1 | 100.00 |
| kmac_csr_rw | 1.570s | 64.827us | 1 | 1 | 100.00 | ||
| kmac_csr_aliasing | 4.100s | 797.041us | 1 | 1 | 100.00 | ||
| kmac_same_csr_outstanding | 1.960s | 167.411us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 21 | 26 | 80.77 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.940s | 79.382us | 0 | 1 | 0.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.940s | 79.382us | 0 | 1 | 0.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.940s | 79.382us | 0 | 1 | 0.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.940s | 79.382us | 0 | 1 | 0.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.390s | 298.962us | 0 | 1 | 0.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.757m | 9.533ms | 1 | 1 | 100.00 |
| kmac_tl_intg_err | 5.260s | 390.371us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.260s | 390.371us | 1 | 1 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 4.240s | 395.705us | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 38.400s | 11.283ms | 1 | 1 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 4.066m | 55.209ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.940s | 79.382us | 0 | 1 | 0.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.757m | 9.533ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.757m | 9.533ms | 1 | 1 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.757m | 9.533ms | 1 | 1 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 38.400s | 11.283ms | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 4.240s | 395.705us | 1 | 1 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.757m | 9.533ms | 1 | 1 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 3.591m | 50.312ms | 1 | 1 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 38.400s | 11.283ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 5 | 60.00 | |||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 4.680s | 585.665us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 32 | 40 | 80.00 |
Job killed! has 5 failures:
Test kmac_long_msg_and_output has 1 failures.
Test kmac_test_vectors_sha3_224 has 1 failures.
Test kmac_test_vectors_sha3_256 has 1 failures.
Test kmac_test_vectors_sha3_384 has 1 failures.
Test kmac_stress_all has 1 failures.
UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 2 failures:
Test kmac_shadow_reg_errors has 1 failures.
0.kmac_shadow_reg_errors.1
Line 85, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log
UVM_FATAL @ 79381857 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 79381857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
0.kmac_shadow_reg_errors_with_csr_rw.1
Line 85, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_FATAL @ 298961733 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
UVM_INFO @ 298961733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/cov_report/cov_report.log
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
0.kmac_stress_all_with_rand_reset.1
Line 80, in log /nightly/runs/opentitan/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 585664740 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
UVM_INFO @ 585664740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---