OTBN Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 0 1 0.00
V1 single_binary otbn_single 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 0 1 0.00
V1 csr_rw otbn_csr_rw 0 1 0.00
V1 csr_bit_bash otbn_csr_bit_bash 0 1 0.00
V1 csr_aliasing otbn_csr_aliasing 0 1 0.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 0 1 0.00
otbn_csr_aliasing 0 1 0.00
V1 mem_walk otbn_mem_walk 0 1 0.00
V1 mem_partial_access otbn_mem_partial_access 0 1 0.00
V1 TOTAL 0 9 0.00
V2 reset_recovery otbn_reset 0 1 0.00
V2 multi_error otbn_multi_err 0 1 0.00
V2 back_to_back otbn_multi 0 1 0.00
V2 stress_all otbn_stress_all 0 1 0.00
V2 lc_escalation otbn_escalate 0 1 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 0 1 0.00
V2 alert_test otbn_alert_test 0 1 0.00
V2 intr_test otbn_intr_test 0 1 0.00
V2 tl_d_oob_addr_access otbn_tl_errors 0 1 0.00
V2 tl_d_illegal_access otbn_tl_errors 0 1 0.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 0 1 0.00
otbn_csr_rw 0 1 0.00
otbn_csr_aliasing 0 1 0.00
otbn_same_csr_outstanding 0 1 0.00
V2 tl_d_partial_access otbn_csr_hw_reset 0 1 0.00
otbn_csr_rw 0 1 0.00
otbn_csr_aliasing 0 1 0.00
otbn_same_csr_outstanding 0 1 0.00
V2 TOTAL 0 11 0.00
V2S mem_integrity otbn_imem_err 0 1 0.00
otbn_dmem_err 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 0 1 0.00
otbn_controller_ispr_rdata_err 0 1 0.00
otbn_mac_bignum_acc_err 0 1 0.00
otbn_urnd_err 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 0 1 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 0 1 0.00
V2S tl_intg_err otbn_sec_cm 0 1 0.00
otbn_tl_intg_err 0 1 0.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 0 1 0.00
V2S prim_fsm_check otbn_sec_cm 0 1 0.00
V2S prim_count_check otbn_sec_cm 0 1 0.00
V2S sec_cm_mem_scramble otbn_smoke 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 0 1 0.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 0 1 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 0 1 0.00
otbn_dmem_err 0 1 0.00
otbn_zero_state_err_urnd 0 1 0.00
otbn_illegal_mem_acc 0 1 0.00
otbn_sec_cm 0 1 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 0 1 0.00
V2S sec_cm_scramble_key_sideload otbn_single 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 0 1 0.00
otbn_dmem_err 0 1 0.00
otbn_zero_state_err_urnd 0 1 0.00
otbn_illegal_mem_acc 0 1 0.00
otbn_sec_cm 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 0 1 0.00
otbn_dmem_err 0 1 0.00
otbn_zero_state_err_urnd 0 1 0.00
otbn_illegal_mem_acc 0 1 0.00
otbn_sec_cm 0 1 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 0 1 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 0 1 0.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 0 1 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 0 1 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 0 1 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 0 1 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 0 1 0.00
V2S sec_cm_key_sideload otbn_single 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 0 1 0.00
V2S TOTAL 0 20 0.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 0 41 0.00

Failure Buckets