PATTGEN Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	6.000s	812.791us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	5.000s	63.591us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	40.791us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	705.491us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	81.291us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	98.191us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	40.791us	1	1	100.00
		pattgen_csr_aliasing	5.000s	81.291us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	21.000s	13.173ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	13.000s	6.607ms	1	1	100.00
V2	error	pattgen_error	5.000s	131.641us	1	1	100.00
V2	stress_all	pattgen_stress_all	5.000s	204.391us	1	1	100.00
V2	alert_test	pattgen_alert_test	5.000s	42.891us	1	1	100.00
V2	intr_test	pattgen_intr_test	5.000s	56.141us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	355.991us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	355.991us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	5.000s	63.591us	1	1	100.00
		pattgen_csr_rw	5.000s	40.791us	1	1	100.00
		pattgen_csr_aliasing	5.000s	81.291us	1	1	100.00
		pattgen_same_csr_outstanding	5.000s	96.191us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	5.000s	63.591us	1	1	100.00
		pattgen_csr_rw	5.000s	40.791us	1	1	100.00
		pattgen_csr_aliasing	5.000s	81.291us	1	1	100.00
		pattgen_same_csr_outstanding	5.000s	96.191us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	6.000s	209.441us	1	1	100.00
		pattgen_sec_cm	6.000s	155.441us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	6.000s	209.441us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	19.000s	8.653ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	5.000s	141.591us	1	1	100.00
		TOTAL			17	18	94.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.06	100.00	100.00	100.00	97.00	93.46	--	98.15	89.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:891) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.1
      Line 110, in log /nightly/runs/opentitan/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 509340573 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 509376621 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 509376621 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 1/5
        UVM_INFO @ 509876621 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]