RV_DM/USE_JTAG_INTERFACE Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.900s 2.553ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.670s 494.058us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.690s 393.298us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 9.100s 14.325ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.900s 897.819us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.320s 7.081ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 4.270s 5.157ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 6.590s 9.587ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 44.030s 77.514ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.220s 1.090ms 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.750s 678.335us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.770s 696.059us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.870s 603.817us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.770s 456.851us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.370s 1.655ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.680s 286.229us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.110s 1.030ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.220s 1.090ms 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 2.070s 480.437us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.080s 933.888us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.770s 696.059us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.700s 135.469us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.150s 301.849us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.280s 227.849us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 23.000s 8.519ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 20.920s 5.995ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.680s 89.089us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 20.920s 5.995ms 1 1 100.00
rv_dm_csr_rw 2.280s 227.849us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.780s 110.400us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.580s 110.400us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 2.900s 2.553ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.160s 697.025us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.950s 537.230us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.740s 470.161us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.490s 1.599ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 7.330s 10.661ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 5.520s 7.116ms 1 1 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 7.620s 10.930ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 28.180s 49.333ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.030s 526.782us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 3.660s 4.126ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.180s 661.300us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.630s 272.056us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 13.480s 19.335ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.810s 89.089us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.790s 278.711us 1 1 100.00
V2 stress_all rv_dm_stress_all 2.470s 1.441ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.390s 108.779us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.720s 79.469us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.720s 79.469us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 20.920s 5.995ms 1 1 100.00
rv_dm_csr_hw_reset 2.150s 301.849us 1 1 100.00
rv_dm_csr_rw 2.280s 227.849us 1 1 100.00
rv_dm_same_csr_outstanding 3.750s 733.990us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 20.920s 5.995ms 1 1 100.00
rv_dm_csr_hw_reset 2.150s 301.849us 1 1 100.00
rv_dm_csr_rw 2.280s 227.849us 1 1 100.00
rv_dm_same_csr_outstanding 3.750s 733.990us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 2.700s 1.114ms 1 1 100.00
rv_dm_tl_intg_err 15.480s 3.218ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 15.480s 3.218ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 3.660s 4.126ms 1 1 100.00
rv_dm_debug_disabled 1.670s 150.883us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 3.660s 4.126ms 1 1 100.00
rv_dm_debug_disabled 1.670s 150.883us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.900s 2.553ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.000s 462.333us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.860s 220.375us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.860s 220.375us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.000s 462.333us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.680s 89.089us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.580s 40.848us 1 1 100.00
TOTAL 48 53 90.57

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
75.65 94.59 83.66 71.96 74.03 86.90 95.74 22.68

Failure Buckets