SYSRST_CTRL Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.230s 2.140ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.520s 2.479ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.520s 2.188ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.550s 2.333ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.220s 4.055ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.410s 2.069ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 19.280s 38.935ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.470s 2.604ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.500s 2.107ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.410s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.470s 2.604ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 38.730s 89.240ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 54.680s 124.368ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.620s 3.034ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 31.940s 1.116s 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.580s 2.538ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.200s 2.176ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.270s 4.403ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.580s 2.627ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.480s 5.148ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.060s 41.727ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 6.080s 12.161ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.130s 2.043ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.210s 2.034ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 2.940s 2.287ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 2.940s 2.287ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.220s 4.055ms 1 1 100.00
sysrst_ctrl_csr_rw 2.410s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.470s 2.604ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.470s 4.669ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.220s 4.055ms 1 1 100.00
sysrst_ctrl_csr_rw 2.410s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.470s 2.604ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.470s 4.669ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 10.930s 22.079ms 1 1 100.00
sysrst_ctrl_tl_intg_err 13.330s 22.422ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 13.330s 22.422ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 7.460s 14.170ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.34 97.79 95.82 100.00 78.85 97.92 93.36 68.64