CHIP Simulation Results

Thursday January 30 2025 22:15:19 UTC

GitHub Revision: 70c7391684

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash			0	1	0.00
		chip_sw_example_rom			0	1	0.00
		chip_sw_example_manufacturer			0	1	0.00
		chip_sw_example_concurrency			0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset			0	1	0.00
V1	csr_rw	chip_csr_rw			0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash			0	1	0.00
V1	csr_aliasing	chip_csr_aliasing			0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing			0	1	0.00
		chip_csr_rw			0	1	0.00
V1	xbar_smoke	xbar_smoke			0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio			0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio			0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio			0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx			0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx			0	1	0.00
		chip_sw_uart_tx_rx_idx1			0	1	0.00
		chip_sw_uart_tx_rx_idx2			0	1	0.00
		chip_sw_uart_tx_rx_idx3			0	1	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate			0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq			0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed			0	1	0.00
V1		TOTAL			0	18	0.00
V2	chip_pin_mux	chip_padctrl_attributes			0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes			0	1	0.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val			0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake			0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention			0	1	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev			0	1	0.00
		chip_tap_straps_testunlock0			0	1	0.00
		chip_tap_straps_rma			0	1	0.00
		chip_tap_straps_prod			0	1	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios			0	1	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses			0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation			0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation			0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en			0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en			0	1	0.00
		chip_sw_aes_enc_jitter_en			0	1	0.00
		chip_sw_edn_entropy_reqs_jitter			0	1	0.00
		chip_sw_hmac_enc_jitter_en			0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en			0	1	0.00
		chip_sw_clkmgr_jitter			0	1	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib			0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert			0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup			0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status			0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup			0	1	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest			0	1	0.00
		chip_sw_aes_smoketest			0	1	0.00
		chip_sw_aon_timer_smoketest			0	1	0.00
		chip_sw_clkmgr_smoketest			0	1	0.00
		chip_sw_csrng_smoketest			0	1	0.00
		chip_sw_entropy_src_smoketest			0	1	0.00
		chip_sw_gpio_smoketest			0	1	0.00
		chip_sw_hmac_smoketest			0	1	0.00
		chip_sw_kmac_smoketest			0	1	0.00
		chip_sw_otbn_smoketest			0	1	0.00
		chip_sw_pwrmgr_smoketest			0	1	0.00
		chip_sw_pwrmgr_usbdev_smoketest			0	1	0.00
		chip_sw_rv_plic_smoketest			0	1	0.00
		chip_sw_rv_timer_smoketest			0	1	0.00
		chip_sw_rstmgr_smoketest			0	1	0.00
		chip_sw_sram_ctrl_smoketest			0	1	0.00
		chip_sw_uart_smoketest			0	1	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest			0	1	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest			0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap			0	1	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke			0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock			0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load			0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load			0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap			0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed			0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors			0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors			0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset			0	1	0.00
		chip_csr_rw			0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing			0	1	0.00
		chip_same_csr_outstanding			0	1	0.00
		chip_csr_hw_reset			0	1	0.00
		chip_csr_rw			0	1	0.00
V2	xbar_base_random_sequence	xbar_random			0	1	0.00
V2	xbar_random_delay	xbar_smoke_zero_delays			0	1	0.00
		xbar_smoke_large_delays			0	1	0.00
		xbar_smoke_slow_rsp			0	1	0.00
		xbar_random_zero_delays			0	1	0.00
		xbar_random_large_delays			0	1	0.00
		xbar_random_slow_rsp			0	1	0.00
V2	xbar_unmapped_address	xbar_unmapped_addr			0	1	0.00
		xbar_error_and_unmapped_addr			0	1	0.00
V2	xbar_error_cases	xbar_error_random			0	1	0.00
		xbar_error_and_unmapped_addr			0	1	0.00
V2	xbar_all_access_same_device	xbar_access_same_device			0	1	0.00
		xbar_access_same_device_slow_rsp			0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source			0	1	0.00
V2	xbar_stress_all	xbar_stress_all			0	1	0.00
		xbar_stress_all_with_error			0	1	0.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset			0	1	0.00
		xbar_stress_all_with_reset_error			0	1	0.00
V2	rom_e2e_smoke	rom_e2e_smoke			0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output			0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c			0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0			0	1	0.00
		rom_e2e_asm_init_dev			0	1	0.00
		rom_e2e_asm_init_prod			0	1	0.00
		rom_e2e_asm_init_prod_end			0	1	0.00
		rom_e2e_asm_init_rma			0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical			0	1	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc			0	1	0.00
		chip_sw_aes_enc_jitter_en			0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy			0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle			0	1	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes			0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test			0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation			0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets			0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0			0	1	0.00
		chip_plic_all_irqs_10			0	1	0.00
		chip_plic_all_irqs_20			0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy			0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info			0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout			0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts			0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff			0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle			0	1	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok			0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep			0	1	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq			0	1	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest			0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq			0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause			0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate			0	1	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness			0	1	0.00
		chip_sw_aes_idle			0	1	0.00
		chip_sw_hmac_enc_idle			0	1	0.00
		chip_sw_kmac_idle			0	1	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans			0	1	0.00
		chip_sw_clkmgr_off_hmac_trans			0	1	0.00
		chip_sw_clkmgr_off_kmac_trans			0	1	0.00
		chip_sw_clkmgr_off_otbn_trans			0	1	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri			0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma			0	1	0.00
		chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc			0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev			0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en			0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en			0	1	0.00
		chip_sw_aes_enc_jitter_en			0	1	0.00
		chip_sw_edn_entropy_reqs_jitter			0	1	0.00
		chip_sw_hmac_enc_jitter_en			0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en			0	1	0.00
		chip_sw_clkmgr_jitter			0	1	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq			0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq			0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq			0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq			0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq			0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq			0	1	0.00
		chip_sw_flash_init_reduced_freq			0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq			0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs			0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency			0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency			0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets			0	1	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff			0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng			0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test			0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test			0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test			0	1	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency			0	1	0.00
		chip_sw_entropy_src_ast_rng_req			0	1	0.00
		chip_sw_edn_entropy_reqs			0	1	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req			0	1	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng			0	1	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test			0	1	0.00
V2	chip_sw_flash_init	chip_sw_flash_init			0	1	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access			0	1	0.00
		chip_sw_flash_ctrl_access_jitter_en			0	1	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops			0	1	0.00
		chip_sw_flash_ctrl_ops_jitter_en			0	1	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked			0	1	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init			0	1	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power			0	1	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation			0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en			0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked			0	1	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en			0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en			0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en			0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en			0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets			0	1	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access			0	1	0.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs			0	1	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert			0	1	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert			0	1	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc			0	1	0.00
		chip_sw_hmac_enc_jitter_en			0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle			0	1	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot			0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream			0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx			0	1	0.00
		chip_sw_i2c_host_tx_rx_idx1			0	1	0.00
		chip_sw_i2c_host_tx_rx_idx2			0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx			0	1	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en			0	1	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac			0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes			0	1	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn			0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake			0	1	0.00
		chip_sw_kmac_mode_kmac			0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en			0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation			0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom			0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy			0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle			0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation			0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev			0	1	0.00
		chip_tap_straps_rma			0	1	0.00
		chip_tap_straps_prod			0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0			0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod			0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en			0	1	0.00
		chip_sw_flash_rma_unlocked			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma			0	1	0.00
		chip_sw_lc_ctrl_transition			0	1	0.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_rom_ctrl_integrity_check			0	1	0.00
		chip_sw_sram_ctrl_execution_main			0	1	0.00
		chip_prim_tl_access			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_lc			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma			0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma			0	1	0.00
		chip_tap_straps_dev			0	1	0.00
		chip_tap_straps_rma			0	1	0.00
		chip_tap_straps_prod			0	1	0.00
		chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap			0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks			0	1	0.00
		chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev			0	1	0.00
		chip_sw_lc_walkthrough_prod			0	1	0.00
		chip_sw_lc_walkthrough_prodend			0	1	0.00
		chip_sw_lc_walkthrough_rma			0	1	0.00
		chip_sw_lc_walkthrough_testunlocks			0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock			0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz			0	1	0.00
		rom_volatile_raw_unlock			0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq			0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en			0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness			0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble			0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init			0	1	0.00
		chip_sw_otbn_mem_scramble			0	1	0.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access			0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate			0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init			0	1	0.00
		chip_sw_otbn_mem_scramble			0	1	0.00
		chip_sw_keymgr_key_derivation			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access			0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate			0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition			0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error			0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0			0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod			0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma			0	1	0.00
		chip_sw_lc_ctrl_transition			0	1	0.00
		chip_prim_tl_access			0	1	0.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access			0	1	0.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock			0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset			0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs			0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset			0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset			0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset			0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset			0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	1	0.00
		chip_sw_pwrmgr_all_reset_reqs			0	1	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req			0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled			0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets			0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check			0	1	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check			0	1	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs			0	1	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs			0	1	0.00
		chip_sw_pwrmgr_wdog_reset			0	1	0.00
		chip_sw_pwrmgr_smoketest			0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req			0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info			0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req			0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info			0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst			0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets			0	1	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle			0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq			0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd			0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation			0	1	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate			0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info			0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info			0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw			0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access			0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req			0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted			0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup			0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma			0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled			0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0			0	1	0.00
		chip_plic_all_irqs_10			0	1	0.00
		chip_plic_all_irqs_20			0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq			0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq			0	1	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke			0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through			0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision			0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm			0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx			0	1	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access			0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en			0	1	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble			0	1	0.00
		chip_sw_sleep_sram_ret_contents_scramble			0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main			0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets			0	1	0.00
		chip_sw_data_integrity_escalation			0	1	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset			0	1	0.00
		chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs			0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs			0	1	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq			0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset			0	1	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l			0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l			0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup			0	1	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus			0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup			0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx			0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg			0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi			0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	1	0.00
V2		TOTAL			0	275	0.00
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off			0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch			0	1	0.00
V2S		TOTAL			0	2	0.00
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0			0	1	0.00
		rom_e2e_jtag_inject_dev			0	1	0.00
		rom_e2e_jtag_inject_rma			0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency			0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode			0	1	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode			0	1	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode			0	1	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat			0	1	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection			0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access			0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation			0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up			0	1	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active			0	1	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs			0	1	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset			0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets			0	1	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	1	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	1	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention			0	1	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx			0	1	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream			0	1	0.00
V3		TOTAL			0	23	0.00
	Unmapped tests	chip_sival_flash_info_access			0	1	0.00
		chip_sw_rstmgr_rst_cnsty_escalation			0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test			0	1	0.00
		chip_sw_otp_ctrl_descrambling			0	1	0.00
		chip_sw_pwrmgr_lowpower_cancel			0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug			0	1	0.00
		chip_sw_flash_ctrl_write_clear			0	1	0.00
		TOTAL			0	325	0.00

Failure Buckets

• Job killed most likely because its dependent job failed. has 327 failures:

  • Test chip_csr_bit_bash has 1 failures.

    • 0.chip_csr_bit_bash.1
      Log /nightly/runs/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

  • Test chip_csr_aliasing has 1 failures.

    • 0.chip_csr_aliasing.1
      Log /nightly/runs/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

  • Test chip_same_csr_outstanding has 1 failures.

    • 0.chip_same_csr_outstanding.1
      Log /nightly/runs/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

  • Test chip_sw_example_flash has 1 failures.

    • 0.chip_sw_example_flash.1
      Log /nightly/runs/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

  • Test chip_sw_example_rom has 1 failures.

    • 0.chip_sw_example_rom.1
      Log /nightly/runs/opentitan/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  • ... and 321 more tests.