CSRNG Simulation Results

Thursday February 06 2025 21:22:13 UTC

GitHub Revision: 89d805bba0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	72.316us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	21.840us	1	1	100.00
V1	csr_rw	csrng_csr_rw	6.000s	27.874us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	13.000s	304.143us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	65.687us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	29.128us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	27.874us	1	1	100.00
		csrng_csr_aliasing	7.000s	65.687us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	9.000s	202.396us	1	1	100.00
V2	alerts	csrng_alert	18.000s	782.916us	1	1	100.00
V2	err	csrng_err	7.000s	35.396us	1	1	100.00
V2	cmds	csrng_cmds	3.217m	17.919ms	1	1	100.00
V2	life cycle	csrng_cmds	3.217m	17.919ms	1	1	100.00
V2	stress_all	csrng_stress_all	4.350m	16.691ms	1	1	100.00
V2	intr_test	csrng_intr_test	6.000s	18.535us	1	1	100.00
V2	alert_test	csrng_alert_test	6.000s	17.400us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	7.000s	68.704us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	7.000s	68.704us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	21.840us	1	1	100.00
		csrng_csr_rw	6.000s	27.874us	1	1	100.00
		csrng_csr_aliasing	7.000s	65.687us	1	1	100.00
		csrng_same_csr_outstanding	7.000s	38.942us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	21.840us	1	1	100.00
		csrng_csr_rw	6.000s	27.874us	1	1	100.00
		csrng_csr_aliasing	7.000s	65.687us	1	1	100.00
		csrng_same_csr_outstanding	7.000s	38.942us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	tl_intg_err	csrng_sec_cm	8.000s	83.145us	1	1	100.00
		csrng_tl_intg_err	8.000s	97.213us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	21.468us	1	1	100.00
		csrng_csr_rw	6.000s	27.874us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	18.000s	782.916us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	4.350m	16.691ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	18.000s	782.916us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	4.350m	16.691ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	18.000s	782.916us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	8.000s	97.213us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
		csrng_sec_cm	8.000s	83.145us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	9.000s	202.396us	1	1	100.00
		csrng_err	7.000s	35.396us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	10.000s	182.144us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			18	19	94.74

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
94.10	96.07	90.48	97.73	93.08	91.71	88.00	92.39	73.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.1
      Line 100, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 182143980 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 182143980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---