OTBN Simulation Results

Thursday February 06 2025 21:22:13 UTC

GitHub Revision: 89d805bba0

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	27.000s	181.441us	1	1	100.00
V1	single_binary	otbn_single	8.000s	42.641us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	46.791us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	52.041us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	245.841us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	65.191us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	125.541us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	6.000s	65.191us	1	1	100.00
V1	mem_walk	otbn_mem_walk	18.000s	3.013ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	896.391us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	17.000s	280.741us	1	1	100.00
V2	multi_error	otbn_multi_err	40.000s	772.091us	1	1	100.00
V2	back_to_back	otbn_multi	33.000s	472.241us	1	1	100.00
V2	stress_all	otbn_stress_all	23.000s	349.891us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	96.821us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	50.191us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	40.391us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	43.191us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	183.591us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	183.591us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	46.791us	1	1	100.00
		otbn_csr_rw	6.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	6.000s	65.191us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	59.541us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	46.791us	1	1	100.00
		otbn_csr_rw	6.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	6.000s	65.191us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	59.541us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	272.891us	1	1	100.00
		otbn_controller_ispr_rdata_err	11.000s	271.154us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	272.297us	1	1	100.00
		otbn_urnd_err	7.000s	29.202us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	28.964us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	42.583us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	30.012us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
		otbn_tl_intg_err	13.000s	294.191us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	470.491us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	27.000s	181.441us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	81.916us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	81.154us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	13.000s	294.191us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	96.821us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	96.821us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	43.821us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	42.393us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	17.000s	267.991us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	17.000s	267.991us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	85.250us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	271.773us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	42.691us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	42.691us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	29.774us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	33.000s	472.241us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	43.041us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.800m	2.644ms	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.333m	5.874ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			40	41	97.56

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.46	93.47	99.58	89.30	89.97	97.44	89.41	63.45

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:891) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.1
      Line 249, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5874140573 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5874140573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---