AES/MASKED Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: 19fa2b599b

Branch: dvsim_scheduler_robustness

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	12.000s	124.516us	1	1	100.00
V1	smoke	aes_smoke	9.000s	110.810us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	69.722us	1	1	100.00
V1	csr_rw	aes_csr_rw	6.000s	68.840us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	672.564us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	195.297us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	71.213us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	68.840us	1	1	100.00
		aes_csr_aliasing	7.000s	195.297us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	9.000s	110.810us	1	1	100.00
		aes_config_error	9.000s	190.575us	1	1	100.00
		aes_stress	9.000s	111.179us	1	1	100.00
V2	key_length	aes_smoke	9.000s	110.810us	1	1	100.00
		aes_config_error	9.000s	190.575us	1	1	100.00
		aes_stress	9.000s	111.179us	1	1	100.00
V2	back2back	aes_stress	9.000s	111.179us	1	1	100.00
		aes_b2b	11.000s	426.196us	1	1	100.00
V2	backpressure	aes_stress	9.000s	111.179us	1	1	100.00
V2	multi_message	aes_smoke	9.000s	110.810us	1	1	100.00
		aes_config_error	9.000s	190.575us	1	1	100.00
		aes_stress	9.000s	111.179us	1	1	100.00
		aes_alert_reset	7.000s	205.399us	1	1	100.00
V2	failure_test	aes_man_cfg_err	11.000s	113.221us	1	1	100.00
		aes_config_error	9.000s	190.575us	1	1	100.00
		aes_alert_reset	7.000s	205.399us	1	1	100.00
V2	trigger_clear_test	aes_clear	7.000s	182.634us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	17.000s	885.051us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	205.399us	1	1	100.00
V2	stress	aes_stress	9.000s	111.179us	1	1	100.00
V2	sideload	aes_stress	9.000s	111.179us	1	1	100.00
		aes_sideload	6.000s	124.516us	1	1	100.00
V2	deinitialization	aes_deinit	12.000s	166.634us	1	1	100.00
V2	stress_all	aes_stress_all	22.000s	1.728ms	1	1	100.00
V2	alert_test	aes_alert_test	7.000s	73.230us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	165.738us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	165.738us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	69.722us	1	1	100.00
		aes_csr_rw	6.000s	68.840us	1	1	100.00
		aes_csr_aliasing	7.000s	195.297us	1	1	100.00
		aes_same_csr_outstanding	5.000s	114.433us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	69.722us	1	1	100.00
		aes_csr_rw	6.000s	68.840us	1	1	100.00
		aes_csr_aliasing	7.000s	195.297us	1	1	100.00
		aes_same_csr_outstanding	5.000s	114.433us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	7.000s	203.076us	1	1	100.00
V2S	fault_inject	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	33.041us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	33.041us	0	1	0.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	33.041us	0	1	0.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	33.041us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	76.771us	0	1	0.00
V2S	tl_intg_err	aes_sec_cm	10.000s	696.902us	1	1	100.00
		aes_tl_intg_err	8.000s	207.916us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	207.916us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	205.399us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	33.041us	0	1	0.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	110.810us	1	1	100.00
		aes_stress	9.000s	111.179us	1	1	100.00
		aes_alert_reset	7.000s	205.399us	1	1	100.00
		aes_core_fi	7.000s	196.575us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	33.041us	0	1	0.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	89.633us	1	1	100.00
		aes_stress	9.000s	111.179us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	111.179us	1	1	100.00
		aes_sideload	6.000s	124.516us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	89.633us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	89.633us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	89.633us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	89.633us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	89.633us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	111.179us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	111.179us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	300.517us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
		aes_ctr_fi	6.000s	77.456us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	300.517us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	6.000s	55.338us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	300.517us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	6.000s	77.456us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
		aes_ctr_fi	6.000s	77.456us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	205.399us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
		aes_ctr_fi	6.000s	77.456us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
		aes_ctr_fi	6.000s	77.456us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	6.000s	77.456us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	300.517us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	6.000s	55.338us	1	1	100.00
V2S		TOTAL			8	11	72.73
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset			0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	32	87.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
94.86	95.53	90.14	96.95	89.95	97.99	93.33	98.80	77.05

Failure Buckets

• Job timed out after * minutes has 2 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

• UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 2 failures:

  • Test aes_shadow_reg_errors has 1 failures.

    • 0.aes_shadow_reg_errors.1
      Line 103, in log /nightly/runs/scratch/dvsim_scheduler_robustness/aes_masked-sim-xcelium/0.aes_shadow_reg_errors/latest/run.log

        UVM_FATAL @  33040991 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @  33040991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test aes_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.aes_shadow_reg_errors_with_csr_rw.1
      Line 103, in log /nightly/runs/scratch/dvsim_scheduler_robustness/aes_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @  76770677 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @  76770677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---