EDN Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: 19fa2b599b

Branch: dvsim_scheduler_robustness

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.480s	41.131us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.780s	56.529us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.630s	44.355us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.340s	557.308us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.930s	94.833us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.700s	79.746us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.630s	44.355us	1	1	100.00
		edn_csr_aliasing	1.930s	94.833us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.650s	48.651us	1	1	100.00
V2	csrng_commands	edn_genbits	1.650s	48.651us	1	1	100.00
V2	genbits	edn_genbits	1.650s	48.651us	1	1	100.00
V2	interrupts	edn_intr	1.700s	28.451us	1	1	100.00
V2	alerts	edn_alert	1.890s	72.611us	1	1	100.00
V2	errs	edn_err	1.830s	33.571us	1	1	100.00
V2	disable	edn_disable	1.720s	27.771us	1	1	100.00
		edn_disable_auto_req_mode	1.710s	43.171us	1	1	100.00
V2	stress_all	edn_stress_all	4.120s	768.811us	1	1	100.00
V2	intr_test	edn_intr_test	1.680s	40.051us	1	1	100.00
V2	alert_test	edn_alert_test	1.560s	49.398us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.940s	296.919us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.940s	296.919us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.780s	56.529us	1	1	100.00
		edn_csr_rw	1.630s	44.355us	1	1	100.00
		edn_csr_aliasing	1.930s	94.833us	1	1	100.00
		edn_same_csr_outstanding	1.680s	80.703us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.780s	56.529us	1	1	100.00
		edn_csr_rw	1.630s	44.355us	1	1	100.00
		edn_csr_aliasing	1.930s	94.833us	1	1	100.00
		edn_same_csr_outstanding	1.680s	80.703us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.990s	1.141ms	1	1	100.00
		edn_tl_intg_err	2.670s	198.832us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.630s	50.011us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.890s	72.611us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.990s	1.141ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.990s	1.141ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.990s	1.141ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.990s	1.141ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.890s	72.611us	1	1	100.00
		edn_sec_cm	6.990s	1.141ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.890s	72.611us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.670s	198.832us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset			0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			20	21	95.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.25	96.09	82.57	77.70	45.93	88.86	97.09	73.48

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes