I2C Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: 19fa2b599b

Branch: dvsim_scheduler_robustness

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.060s	8.464ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.690s	3.356ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.720s	76.744us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.680s	74.369us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.440s	1.875ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.450s	407.830us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.740s	123.661us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.680s	74.369us	1	1	100.00
		i2c_csr_aliasing	2.450s	407.830us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.090s	392.080us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.710m	26.785ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	7.440s	3.263ms	1	1	100.00
V2	host_override	i2c_host_override	1.450s	48.410us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	43.210s	13.741ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	29.060s	7.147ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.740s	340.121us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.890s	1.334ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.320s	563.956us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	23.110s	7.050ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.270s	2.003ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.840s	273.412us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.170s	8.204ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.547m	57.098ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.580s	2.273ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	4.470s	1.188ms	1	1	100.00
		i2c_target_intr_smoke	3.670s	3.039ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.950s	585.790us	1	1	100.00
		i2c_target_fifo_reset_tx	1.850s	549.248us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	5.410s	12.126ms	1	1	100.00
		i2c_target_stress_rd	4.470s	1.188ms	1	1	100.00
		i2c_target_intr_stress_wr	3.420s	4.974ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.720s	5.028ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.940s	927.959us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.300s	2.715ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.270s	1.096ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.610s	1.816ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.730s	406.038us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	7.440s	3.263ms	1	1	100.00
		i2c_host_perf_precise	1.750s	57.577us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.270s	2.003ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.200s	232.079us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.710s	2.013ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.470s	1.977ms	1	1	100.00
		i2c_target_nack_txstretch	2.170s	520.414us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.920s	764.166us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.340s	1.843ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.580s	49.619us	1	1	100.00
V2	intr_test	i2c_intr_test	1.630s	49.827us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.030s	624.748us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.030s	624.748us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.720s	76.744us	1	1	100.00
		i2c_csr_rw	1.680s	74.369us	1	1	100.00
		i2c_csr_aliasing	2.450s	407.830us	1	1	100.00
		i2c_same_csr_outstanding	1.860s	199.578us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.720s	76.744us	1	1	100.00
		i2c_csr_rw	1.680s	74.369us	1	1	100.00
		i2c_csr_aliasing	2.450s	407.830us	1	1	100.00
		i2c_same_csr_outstanding	1.860s	199.578us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	4.080s	510.331us	1	1	100.00
		i2c_sec_cm	2.760s	259.037us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	4.080s	510.331us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.940s	1.972ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.330s	1.271ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	5.470s	1.805ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.05	96.37	86.47	77.78	69.64	92.62	98.30	81.16

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.1
      Line 172, in log /nightly/runs/scratch/dvsim_scheduler_robustness/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 26785165929 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @2005348
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.1
      Line 74, in log /nightly/runs/scratch/dvsim_scheduler_robustness/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 1271045223 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 1271045223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:890) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.1
      Line 82, in log /nightly/runs/scratch/dvsim_scheduler_robustness/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1971884163 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1971884163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.1
      Line 95, in log /nightly/runs/scratch/dvsim_scheduler_robustness/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1805341164 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 70 [0x46])
        UVM_INFO @ 1805341164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---