KMAC/MASKED Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: `19fa2b599b`

Branch: dvsim_scheduler_robustness

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	53.080s	13.473ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.630s	59.077us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.670s	64.827us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.480s	2.020ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.210s	797.041us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.140s	172.578us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.670s	64.827us	1	1	100.00
		kmac_csr_aliasing	4.210s	797.041us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.580s	36.952us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.690s	103.036us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	42.735m	367.203ms	1	1	100.00
V2	burst_write	kmac_burst_write	15.212m	111.415ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.602m	259.702ms	1	1	100.00
		kmac_test_vectors_sha3_256	25.717m	239.727ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.381m	182.070ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.983m	132.282ms	1	1	100.00
		kmac_test_vectors_shake_128	2.747m	52.297ms	1	1	100.00
		kmac_test_vectors_shake_256	4.523m	74.754ms	1	1	100.00
		kmac_test_vectors_kmac	2.910s	349.538us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.890s	277.621us	1	1	100.00
V2	sideload	kmac_sideload	5.221m	59.193ms	1	1	100.00
V2	app	kmac_app	3.620m	44.980ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.001m	53.162ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.379m	55.894ms	1	1	100.00
V2	error	kmac_error	5.033m	56.280ms	1	1	100.00
V2	key_error	kmac_key_error	7.540s	3.780ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.400s	350.371us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	27.470s	5.688ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.730s	136.536us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	48.580s	20.406ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	5.210s	454.289us	1	1	100.00
V2	stress_all	kmac_stress_all	25.791m	254.651ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.390s	33.452us	1	1	100.00
V2	alert_test	kmac_alert_test	1.450s	41.660us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.170s	228.412us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.170s	228.412us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.630s	59.077us	1	1	100.00
		kmac_csr_rw	1.670s	64.827us	1	1	100.00
		kmac_csr_aliasing	4.210s	797.041us	1	1	100.00
		kmac_same_csr_outstanding	2.040s	167.411us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.630s	59.077us	1	1	100.00
		kmac_csr_rw	1.670s	64.827us	1	1	100.00
		kmac_csr_aliasing	4.210s	797.041us	1	1	100.00
		kmac_same_csr_outstanding	2.040s	167.411us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.940s	79.382us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.940s	79.382us	0	1	0.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.940s	79.382us	0	1	0.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.940s	79.382us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.540s	298.962us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	3.769m	13.106ms	1	1	100.00
		kmac_tl_intg_err	5.010s	390.371us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.010s	390.371us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	5.210s	454.289us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	53.080s	13.473ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.221m	59.193ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.940s	79.382us	0	1	0.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	3.769m	13.106ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	3.769m	13.106ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	3.769m	13.106ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	53.080s	13.473ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	5.210s	454.289us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	3.769m	13.106ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.037m	47.631ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	53.080s	13.473ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.770s	592.456us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.76	98.61	89.18	99.76	63.38	96.03	97.30	91.08

Failure Buckets

UVM_FATAL (alert_receiver_driver.sv:145) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 2 failures:

Test kmac_shadow_reg_errors has 1 failures.

0.kmac_shadow_reg_errors.1
Line 75, in log /nightly/runs/scratch/dvsim_scheduler_robustness/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

  UVM_FATAL @  79381857 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @  79381857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

0.kmac_shadow_reg_errors_with_csr_rw.1
Line 75, in log /nightly/runs/scratch/dvsim_scheduler_robustness/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

  UVM_FATAL @ 298961733 ps: (alert_receiver_driver.sv:145) [uvm_test_top.env.m_alert_agent_fatal_fault_err.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
  UVM_INFO @ 298961733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.1
    Line 80, in log /nightly/runs/scratch/dvsim_scheduler_robustness/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 592456461 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 592456461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```