OTBN Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: 19fa2b599b

Branch: dvsim_scheduler_robustness

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	181.441us	1	1	100.00
V1	single_binary	otbn_single	8.000s	42.641us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	46.791us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	52.041us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	245.841us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	39.205m		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
V1	mem_walk	otbn_mem_walk	18.000s	3.013ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	896.391us	1	1	100.00
V1		TOTAL			8	9	88.89
V2	reset_recovery	otbn_reset	46.789m		0	1	0.00
V2	multi_error	otbn_multi_err	41.000s	772.091us	1	1	100.00
V2	back_to_back	otbn_multi	35.000s	472.241us	1	1	100.00
V2	stress_all	otbn_stress_all			0	1	0.00
V2	lc_escalation	otbn_escalate			0	1	0.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	50.191us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	40.391us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	43.191us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	183.591us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	183.591us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	46.791us	1	1	100.00
		otbn_csr_rw	7.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	59.541us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	46.791us	1	1	100.00
		otbn_csr_rw	7.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	59.541us	1	1	100.00
V2		TOTAL			8	11	72.73
V2S	mem_integrity	otbn_imem_err	11.000s	81.154us	1	1	100.00
		otbn_dmem_err	11.000s	81.916us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	272.891us	1	1	100.00
		otbn_controller_ispr_rdata_err	12.000s	271.154us	1	1	100.00
		otbn_mac_bignum_acc_err	12.000s	272.297us	1	1	100.00
		otbn_urnd_err	7.000s	29.202us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	42.583us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	30.012us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
		otbn_tl_intg_err	14.000s	294.191us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	24.000s	470.491us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	181.441us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	81.916us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	81.154us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	14.000s	294.191us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate			0	1	0.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	81.154us	1	1	100.00
		otbn_dmem_err	11.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	81.154us	1	1	100.00
		otbn_dmem_err	11.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate			0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	81.154us	1	1	100.00
		otbn_dmem_err	11.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun			0	1	0.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	42.393us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	17.000s	267.991us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	17.000s	267.991us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	85.250us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	271.773us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	42.691us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	42.691us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	29.774us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	35.000s	472.241us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	43.041us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.867m	2.644ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.467h		0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			35	41	85.37

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.32	99.43	93.07	99.55	87.97	88.57	97.44	88.72	60.92

Failure Buckets

• Job returned non-zero exit code has 3 failures:

  • Test otbn_reset has 1 failures.

    • 0.otbn_reset.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/otbn-sim-xcelium/0.otbn_reset/latest/run.log

        >   if {$simulator eq "xcelium"} {
        >     # Xcelium provides a `finish` tcl command instead of `quit`. The argument '2' enables the
        >     # logging of additional resource usage information.
        >     finish 2
        >   } else {
        >     quit
        >   }
        > }
        UVM_INFO @ 0 ps: reporter [RNTST] Running test otbn_base_test...
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:191: simulate] Killed
      

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        >   if {$simulator eq "xcelium"} {
        >     # Xcelium provides a `finish` tcl command instead of `quit`. The argument '2' enables the
        >     # logging of additional resource usage information.
        >     finish 2
        >   } else {
        >     quit
        >   }
        > }
        UVM_INFO @ 0 ps: reporter [RNTST] Running test otbn_base_test...
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:191: simulate] Killed
      

  • Test otbn_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.otbn_csr_mem_rw_with_rand_reset.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/otbn-sim-xcelium/0.otbn_csr_mem_rw_with_rand_reset/latest/run.log

        >   if {$simulator eq "xcelium"} {
        >     # Xcelium provides a `finish` tcl command instead of `quit`. The argument '2' enables the
        >     # logging of additional resource usage information.
        >     finish 2
        >   } else {
        >     quit
        >   }
        > }
        UVM_INFO @ 0 ps: reporter [RNTST] Running test otbn_base_test...
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:191: simulate] Killed
      

• Job timed out after * minutes has 3 failures:

  • Test otbn_escalate has 1 failures.

    • 0.otbn_escalate.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/otbn-sim-xcelium/0.otbn_escalate/latest/run.log

        Job timed out after 60 minutes
      

  • Test otbn_stress_all has 1 failures.

    • 0.otbn_stress_all.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/otbn-sim-xcelium/0.otbn_stress_all/latest/run.log

        Job timed out after 180 minutes
      

  • Test otbn_ctrl_redun has 1 failures.

    • 0.otbn_ctrl_redun.1
      Log /nightly/runs/scratch/dvsim_scheduler_robustness/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

        Job timed out after 60 minutes