PATTGEN Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: 19fa2b599b

Branch: dvsim_scheduler_robustness

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 11.000s 812.791us 1 1 100.00
V1 csr_hw_reset pattgen_csr_hw_reset 5.000s 63.591us 1 1 100.00
V1 csr_rw pattgen_csr_rw 6.000s 40.791us 1 1 100.00
V1 csr_bit_bash pattgen_csr_bit_bash 6.000s 705.491us 1 1 100.00
V1 csr_aliasing pattgen_csr_aliasing 6.000s 81.291us 1 1 100.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 6.000s 40.791us 1 1 100.00
pattgen_csr_aliasing 6.000s 81.291us 1 1 100.00
V1 TOTAL 5 6 83.33
V2 perf pattgen_perf 25.000s 13.173ms 1 1 100.00
V2 cnt_rollover cnt_rollover 17.000s 6.607ms 1 1 100.00
V2 error pattgen_error 10.000s 131.641us 1 1 100.00
V2 stress_all pattgen_stress_all 7.000s 204.391us 1 1 100.00
V2 alert_test pattgen_alert_test 7.000s 42.891us 1 1 100.00
V2 intr_test pattgen_intr_test 5.000s 56.141us 1 1 100.00
V2 tl_d_oob_addr_access pattgen_tl_errors 8.000s 355.991us 1 1 100.00
V2 tl_d_illegal_access pattgen_tl_errors 8.000s 355.991us 1 1 100.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 5.000s 63.591us 1 1 100.00
pattgen_csr_rw 6.000s 40.791us 1 1 100.00
pattgen_csr_aliasing 6.000s 81.291us 1 1 100.00
pattgen_same_csr_outstanding 6.000s 96.191us 1 1 100.00
V2 tl_d_partial_access pattgen_csr_hw_reset 5.000s 63.591us 1 1 100.00
pattgen_csr_rw 6.000s 40.791us 1 1 100.00
pattgen_csr_aliasing 6.000s 81.291us 1 1 100.00
pattgen_same_csr_outstanding 6.000s 96.191us 1 1 100.00
V2 TOTAL 8 8 100.00
V2S tl_intg_err pattgen_tl_intg_err 8.000s 209.441us 1 1 100.00
pattgen_sec_cm 9.000s 155.441us 1 1 100.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 8.000s 209.441us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests pattgen_inactive_level 9.000s 141.591us 1 1 100.00
TOTAL 16 18 88.89

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.06 100.00 100.00 100.00 97.00 93.46 -- 98.15 89.47

Failure Buckets