CHIP Simulation Results

Monday February 10 2025 18:13:12 UTC

GitHub Revision: `19fa2b599b`

Branch: dvsim_scheduler_robustness

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.799m	2.836ms	1	1	100.00
		chip_sw_example_rom	1.049m	2.517ms	1	1	100.00
		chip_sw_example_manufacturer	1.700m	2.836ms	1	1	100.00
		chip_sw_example_concurrency	1.953m	2.895ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.899m	4.494ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.212m	4.043ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.599m	8.463ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	43.671m	31.903ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	41.950s	2.420ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	43.671m	31.903ms	1	1	100.00
		chip_csr_rw	2.212m	4.043ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.710s	185.153us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	2.365m	3.055ms	0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	2.365m	3.055ms	0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	2.365m	3.055ms	0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.625m	4.354ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.625m	4.354ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.742m	4.354ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.702m	4.354ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.770m	4.354ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	3.942m	3.899ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.362m	3.951ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.502m	4.142ms	1	1	100.00
V1		TOTAL			16	18	88.89
V2	chip_pin_mux	chip_padctrl_attributes	1.962m	4.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.962m	4.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.291m	3.143ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.279m	5.564ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.469m	3.813ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.449m	2.925ms	1	1	100.00
		chip_tap_straps_testunlock0	3.780m	5.482ms	1	1	100.00
		chip_tap_straps_rma	3.795m	5.482ms	1	1	100.00
		chip_tap_straps_prod	1.402m	2.925ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.022m	2.958ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	9.772m	8.736ms	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.151m	5.301ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.151m	5.301ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.073m	7.425ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	30.502m	21.428ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.966m	4.320ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.146m	6.079ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	45.232m	18.858ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.139m	3.021ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.107m	6.221ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.130m	3.022ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.965m	9.550ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.351m	3.110ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.402m	4.479ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.838m	2.841ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.640m	3.150ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.776m	6.746ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.464m	5.328ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.223m	2.941ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.464m	5.328ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.869m	2.841ms	1	1	100.00
		chip_sw_aes_smoketest	2.204m	2.998ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.311m	3.116ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.797m	2.871ms	1	1	100.00
		chip_sw_csrng_smoketest	1.864m	2.866ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.513m	3.614ms	1	1	100.00
		chip_sw_gpio_smoketest	2.033m	2.931ms	0	1	0.00
		chip_sw_hmac_smoketest	2.581m	3.258ms	1	1	100.00
		chip_sw_kmac_smoketest	2.364m	3.062ms	1	1	100.00
		chip_sw_otbn_smoketest	13.251m	8.326ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.178m	5.526ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.353m	5.519ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.865m	2.878ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.070m	3.014ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.740m	2.838ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.839m	2.862ms	1	1	100.00
		chip_sw_uart_smoketest	2.122m	3.008ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.084m	2.996ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.295m	4.431ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.608h	83.281ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.983m	15.478ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.106m	5.249ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	5.216m	4.419ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.757m	10.214ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.077h	63.364ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.286h	69.880ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	38.050s	2.419ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	38.050s	2.419ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	43.671m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	12.945m	15.303ms	1	1	100.00
		chip_csr_hw_reset	1.899m	4.494ms	1	1	100.00
		chip_csr_rw	2.212m	4.043ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	43.671m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	12.945m	15.303ms	1	1	100.00
		chip_csr_hw_reset	1.899m	4.494ms	1	1	100.00
		chip_csr_rw	2.212m	4.043ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	45.000s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.750s	51.903us	1	1	100.00
		xbar_smoke_large_delays	43.360s	7.416ms	1	1	100.00
		xbar_smoke_slow_rsp	37.120s	4.510ms	1	1	100.00
		xbar_random_zero_delays	29.340s	587.063us	1	1	100.00
		xbar_random_large_delays	5.205m	54.598ms	1	1	100.00
		xbar_random_slow_rsp	4.581m	33.551ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.810s	1.309ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.060s	1.303ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	41.510s	2.371ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.060s	1.303ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	48.320s	2.200ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.832m	64.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	18.260s	1.063ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.165m	3.101ms	1	1	100.00
		xbar_stress_all_with_error	56.810s	3.101ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.251m	7.159ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.437m	7.159ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.983m	15.478ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.759m	25.471ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.371m	14.939ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.881m	11.911ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.723m	16.271ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.189m	16.271ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.410m	16.271ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.492m	15.571ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	24.950s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	25.290s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	25.070s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.260s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	25.960s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.600s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	26.140s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	25.640s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.570s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.300s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.020s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.260s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.100s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.620s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.330s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.740s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.850s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.630s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.880s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.230s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.590s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.670s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.630s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.910s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	25.490s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.959m	11.915ms	1	1	100.00
		rom_e2e_asm_init_dev	39.272m	16.282ms	1	1	100.00
		rom_e2e_asm_init_prod	40.178m	16.282ms	1	1	100.00
		rom_e2e_asm_init_prod_end	39.226m	16.281ms	1	1	100.00
		rom_e2e_asm_init_rma	37.110m	15.581ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	37.413m	15.777ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.241m	15.734ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.339m	15.734ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.677m	17.987ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.266m	18.614ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.266m	18.614ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.218m	2.998ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.139m	3.021ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.092m	2.931ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.142m	2.920ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.657m	9.677ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.314m	3.152ms	1	1	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.082m	4.827ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.830m	6.107ms	1	1	100.00
		chip_plic_all_irqs_10	4.487m	4.004ms	1	1	100.00
		chip_plic_all_irqs_20	6.519m	4.813ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.469m	3.207ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.399m	11.605ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.910m	4.933ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.280m	3.820ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.065m	12.275ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.575m	7.992ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.000m	7.848ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	10.476m	7.992ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.005h	255.097ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.252m	4.004ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.178m	5.526ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.252m	4.004ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.345m	7.932ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.345m	7.932ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.533m	6.780ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.463m	4.963ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.333m	6.015ms	1	1	100.00
		chip_sw_aes_idle	2.142m	2.920ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.148m	3.033ms	1	1	100.00
		chip_sw_kmac_idle	1.996m	2.921ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.349m	4.111ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.404m	4.111ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.293m	4.111ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.358m	4.111ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.994m	9.528ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	4.920m	4.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.334m	4.795ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.234m	4.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.252m	4.795ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.443m	4.122ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.983m	4.795ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.073m	7.425ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.968m	5.772ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.234m	4.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.252m	4.795ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.966m	4.320ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.146m	6.079ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	45.232m	18.858ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.139m	3.021ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.107m	6.221ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.130m	3.022ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.965m	9.550ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.351m	3.110ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.402m	4.479ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.838m	2.841ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.677m	2.856ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.209m	4.970ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.631m	7.488ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.913m	25.025ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.967m	3.115ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.067m	3.116ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.558m	9.717ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.206m	3.243ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.373m	4.680ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	14.906m	19.250ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.577h	68.214ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.073m	7.425ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.940m	4.705ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.287m	3.518ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.575m	7.992ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.505m	6.687ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	3.756m	4.180ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.909m	5.883ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.007m	2.901ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	39.738m	17.649ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.952m	2.868ms	1	1	100.00
		chip_sw_edn_entropy_reqs	7.690m	6.158ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.952m	2.868ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.505m	6.687ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.986m	2.869ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.327m	17.947ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	7.773m	5.717ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.146m	6.079ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.617m	4.153ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.966m	4.320ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	45.795m	43.259ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.327m	17.947ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.912m	3.518ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.548m	9.510ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.599m	4.544ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	45.795m	43.259ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.599m	4.544ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.599m	4.544ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.599m	4.544ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.599m	4.544ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.675m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.136m	5.694ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.358m	5.020ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.358m	5.020ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.082m	2.998ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.130m	3.022ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.148m	3.033ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.512m	3.137ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	11.342m	6.830ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.090m	5.439ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.341m	5.439ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.406m	5.439ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.155m	4.169ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.548m	9.510ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.965m	9.550ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	14.212m	9.581ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.657m	9.677ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.437m	14.332ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.036m	2.901ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.371m	3.077ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.351m	3.110ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.548m	9.510ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.943m	2.852ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.351m	8.288ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.996m	2.921ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.082m	4.827ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.449m	2.925ms	1	1	100.00
		chip_tap_straps_rma	3.795m	5.482ms	1	1	100.00
		chip_tap_straps_prod	1.402m	2.925ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.215m	3.068ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	14.670m	9.505ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.599m	4.544ms	1	1	100.00
		chip_sw_flash_rma_unlocked	45.795m	43.259ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.870m	4.443ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.012m	7.432ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.359m	7.437ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.283m	7.437ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.548m	9.510ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.747m	8.860ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.175m	7.308ms	1	1	100.00
		chip_prim_tl_access	1.675m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.968m	5.772ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	4.920m	4.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.334m	4.795ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.234m	4.123ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.252m	4.795ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.443m	4.122ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.983m	4.795ms	1	1	100.00
		chip_tap_straps_dev	1.449m	2.925ms	1	1	100.00
		chip_tap_straps_rma	3.795m	5.482ms	1	1	100.00
		chip_tap_straps_prod	1.402m	2.925ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.765m	10.388ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.146m	3.469ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.242m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.214m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.218m	3.372ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	15.882m	23.926ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.765m	10.388ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	53.177m	47.620ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	52.595m	47.620ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.962m	8.510ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	52.930m	46.130ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	15.882m	23.926ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	57.420s	2.488ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	59.920s	2.532ms	1	1	100.00
		rom_volatile_raw_unlock	1.052m	2.532ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	47.391m	17.240ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	45.232m	18.858ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.333m	6.015ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.333m	6.015ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.333m	6.015ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.822m	3.673ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.327m	17.947ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.822m	3.673ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.548m	9.510ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.316m	4.423ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.881m	2.916ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.327m	17.947ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.822m	3.673ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.548m	9.510ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.316m	4.423ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.881m	2.916ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.008m	4.574ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.215m	3.068ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.870m	4.443ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	10.012m	7.432ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.359m	7.437ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.283m	7.437ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.677m	5.747ms	1	1	100.00
		chip_prim_tl_access	1.675m	4.853ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.675m	4.853ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	51.342m	27.203ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.075m	7.675ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.213m	21.141ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.290m	7.478ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.714m	7.753ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.363m	5.937ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.700m	21.742ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.884m	13.579ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.345m	7.932ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.551m	10.484ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.218m	4.486ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.075m	7.675ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.134m	4.071ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.151m	30.671ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.516m	6.221ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	1.851m	2.999ms	0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.580m	20.990ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.134m	6.894ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.452m	9.974ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.226m	22.939ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.180m	3.138ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.747m	8.860ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.747m	8.860ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.452m	9.974ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.580m	20.990ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.218m	4.486ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.178m	5.526ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.188m	3.998ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.956m	4.093ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.171m	3.980ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.399m	11.605ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.948m	2.881ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.000m	7.848ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.255m	4.936ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.509m	5.594ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.394m	3.035ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.881m	2.916ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.956m	4.093ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.956m	4.093ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.231m	9.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.458m	13.888ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.188m	3.998ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.602m	4.291ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.891m	5.778ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.795m	5.482ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.765m	10.388ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.830m	6.107ms	1	1	100.00
		chip_plic_all_irqs_10	4.487m	4.004ms	1	1	100.00
		chip_plic_all_irqs_20	6.519m	4.813ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.205m	2.971ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.016m	3.014ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.983m	15.478ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.938m	6.787ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.246m	4.349ms	1	1	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.841m	3.471ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.334m	3.043ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.316m	4.423ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.402m	4.479ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.799m	7.143ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.339m	7.276ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.175m	7.308ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.151m	5.301ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.134m	6.894ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.546m	22.619ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.404m	3.146ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.938m	3.689ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.810m	4.777ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.546m	22.619ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.546m	22.619ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	31.261m	20.959ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	31.261m	20.959ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.593m	5.707ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.266m	18.614ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.895m	2.885ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.277m	3.073ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.681m	3.744ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.104m	3.953ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	14.146m	8.175ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.160h	31.743ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	22.598m	12.145ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.182m	2.976ms	1	1	100.00
V2		TOTAL			243	275	88.36
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.581m	3.067ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.043m	2.825ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.360h	71.670ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.476m	5.727ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.322m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.296m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.944m	11.323ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	33.719m	36.811ms	1	1	100.00
		rom_e2e_jtag_inject_dev	34.277m	36.811ms	1	1	100.00
		rom_e2e_jtag_inject_rma	33.977m	36.811ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.009s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	3.204m	3.526ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.219m	2.823ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.266m	4.463ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.738m	8.173ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	5.140m	3.216ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.801m	5.725ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	54.470s	2.427ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	7.382m	13.086ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.381m	5.597ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.794m	4.468ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.452m	9.974ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.322m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.296m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.944m	11.323ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.014s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.775m	5.019ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.345h	38.420ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.345h	38.420ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.360m	3.527ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.625m	4.354ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	38.265m	19.034ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.388m	3.136ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.762m	5.021ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.131m	2.968ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	4.832m	4.129ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.143m	3.916ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.012s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.789m	3.186ms	1	1	100.00
		TOTAL			286	325	88.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.44	95.01	88.84	93.09	--	93.70	96.72	45.28

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1
    Line 494, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1
    Line 513, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1
    Line 507, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1
    Line 508, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1
    Line 496, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1
Line 484, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1
Line 484, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1
Line 485, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1
Line 499, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1
Line 484, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 3 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.1
Log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.110s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rv_dm_access_after_escalation_reset has 1 failures.

0.chip_sw_rv_dm_access_after_escalation_reset.1
Log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 0.096s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1
Log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.117s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1
    Line 462, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1
    Line 469, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1
    Line 457, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1
    Line 515, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1
    Line 476, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1
    Line 522, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1
    Line 527, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_pwm_pulses_vseq.sv:55) virtual_sequencer [chip_sw_pwm_pulses_vseq] PWMCH* : lowpower counter is zero has 1 failures:
- Test chip_sw_sleep_pwm_pulses has 1 failures.
  - 0.chip_sw_sleep_pwm_pulses.1
    Line 424, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  UVM_ERROR @ 8735.626500 us: (chip_sw_pwm_pulses_vseq.sv:55) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_pwm_pulses_vseq] PWMCH0 : lowpower counter is zero
  UVM_INFO @ 8735.626500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = *, read = *) has 1 failures:
- Test chip_sw_gpio has 1 failures.
  - 0.chip_sw_gpio.1
    Line 415, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest/run.log
```
  UVM_ERROR @ 3055.020540 us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = 1, read = 0)
  UVM_INFO @ 3055.020540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done. has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.1
    Line 413, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_FATAL @ 13086.360540 us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done.
  UVM_INFO @ 13086.360540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:515) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@110109) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 431, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4092.703916 us: (cip_base_scoreboard.sv:515) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@110109) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4092.703916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (rom_ctrl_fsm.sv:212) [ASSERT FAILED] SecCmCFILinear_A has 1 failures:
- Test chip_sw_pwrmgr_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1
    Line 422, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
```
  UVM_ERROR @ 2999.488928 us: (rom_ctrl_fsm.sv:212) [ASSERT FAILED] SecCmCFILinear_A
  UVM_INFO @ 2999.488928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:515) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 230, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2419.289116 us: (cip_base_scoreboard.sv:515) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h106e8  a_data: 'h65c994b0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18abe  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2419.289116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.1
    Line 427, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2825.025540 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2825.025540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:104) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.1
    Line 420, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 4419.400540 us: (chip_sw_power_idle_load_vseq.sv:104) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 4419.400540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:127) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1
    Line 440, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 10214.254088 us: (chip_sw_power_sleep_load_vseq.sv:127) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 10214.254088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1
    Line 493, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1
    Line 483, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_smoketest_sim_dv(sw/device/tests/gpio_smoketest.c:57)] CHECK-fail: * != *fe8c* has 1 failures:
- Test chip_sw_gpio_smoketest has 1 failures.
  - 0.chip_sw_gpio_smoketest.1
    Line 415, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest/run.log
```
  UVM_ERROR @ 2931.240540 us: (sw_logger_if.sv:526) [gpio_smoketest_sim_dv(sw/device/tests/gpio_smoketest.c:57)] CHECK-fail: 250fe8c6 != 250fe8c2
  UVM_INFO @ 2931.240540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:515) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1
Line 237, in log /nightly/runs/scratch/dvsim_scheduler_robustness/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2420.279116 us: (cip_base_scoreboard.sv:515) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: 'h104fc  a_data: 'hb08d55f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a9be  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2420.279116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---