| V1 |
smoke |
gpio_smoke |
1.940s |
266.954us |
1 |
1 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown |
1.930s |
266.954us |
1 |
1 |
100.00 |
|
|
gpio_smoke_en_cdc_prim |
1.920s |
272.871us |
1 |
1 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown_en_cdc_prim |
1.930s |
272.871us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
gpio_csr_hw_reset |
1.460s |
56.535us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
gpio_csr_rw |
1.350s |
44.160us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
gpio_csr_bit_bash |
2.740s |
707.457us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
gpio_csr_aliasing |
1.670s |
90.536us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
gpio_csr_mem_rw_with_rand_reset |
1.770s |
114.119us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
gpio_csr_rw |
1.350s |
44.160us |
1 |
1 |
100.00 |
|
|
gpio_csr_aliasing |
1.670s |
90.536us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
9 |
9 |
100.00 |
| V2 |
direct_and_masked_out |
gpio_random_dout_din |
1.700s |
141.369us |
1 |
1 |
100.00 |
|
|
gpio_random_dout_din_no_pullup_pulldown |
1.690s |
141.369us |
1 |
1 |
100.00 |
| V2 |
out_in_regs_read_write |
gpio_dout_din_regs_random_rw |
1.550s |
127.203us |
1 |
1 |
100.00 |
| V2 |
gpio_interrupt_programming |
gpio_intr_rand_pgm |
1.780s |
235.370us |
1 |
1 |
100.00 |
| V2 |
random_interrupt_trigger |
gpio_rand_intr_trigger |
2.430s |
395.580us |
1 |
1 |
100.00 |
| V2 |
interrupt_and_noise_filter |
gpio_intr_with_filter_rand_intr_event |
2.660s |
231.620us |
1 |
1 |
100.00 |
| V2 |
noise_filter_stress |
gpio_filter_stress |
11.180s |
1.930ms |
1 |
1 |
100.00 |
| V2 |
regs_long_reads_and_writes |
gpio_random_long_reg_writes_reg_reads |
3.620s |
921.542us |
1 |
1 |
100.00 |
| V2 |
full_random |
gpio_full_random |
1.760s |
207.953us |
1 |
1 |
100.00 |
| V2 |
stress_all |
gpio_stress_all |
1.688m |
44.645ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
gpio_alert_test |
1.370s |
45.785us |
1 |
1 |
100.00 |
| V2 |
intr_test |
gpio_intr_test |
1.490s |
40.785us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
gpio_tl_errors |
2.740s |
443.330us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
gpio_tl_errors |
2.740s |
443.330us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
gpio_csr_rw |
1.350s |
44.160us |
1 |
1 |
100.00 |
|
|
gpio_same_csr_outstanding |
1.450s |
99.077us |
1 |
1 |
100.00 |
|
|
gpio_csr_aliasing |
1.670s |
90.536us |
1 |
1 |
100.00 |
|
|
gpio_csr_hw_reset |
1.460s |
56.535us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
gpio_csr_rw |
1.350s |
44.160us |
1 |
1 |
100.00 |
|
|
gpio_same_csr_outstanding |
1.450s |
99.077us |
1 |
1 |
100.00 |
|
|
gpio_csr_aliasing |
1.670s |
90.536us |
1 |
1 |
100.00 |
|
|
gpio_csr_hw_reset |
1.460s |
56.535us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
14 |
14 |
100.00 |
| V2S |
tl_intg_err |
gpio_tl_intg_err |
2.890s |
306.829us |
1 |
1 |
100.00 |
|
|
gpio_sec_cm |
2.650s |
254.579us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
gpio_tl_intg_err |
2.890s |
306.829us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
stress_all_with_rand_reset |
gpio_stress_all_with_rand_reset |
44.420s |
15.893ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
26 |
26 |
100.00 |