SYSRST_CTRL Simulation Results

Tuesday March 11 2025 20:24:04 UTC

GitHub Revision: ee102588db

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.230s 2.140ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.560s 2.479ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.490s 2.188ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.600s 2.333ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 3.290s 4.055ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.440s 2.069ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 19.240s 38.935ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 3.480s 2.604ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.560s 2.108ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.440s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.480s 2.604ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 40.350s 89.215ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 54.410s 124.363ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.820s 3.034ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 32.580s 1.116s 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.700s 2.538ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.480s 2.176ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 3.370s 4.403ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 2.690s 2.627ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.380s 5.148ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.270s 41.727ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 6.110s 12.161ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.370s 2.043ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 2.310s 2.034ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.130s 2.287ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.130s 2.287ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 3.290s 4.055ms 1 1 100.00
sysrst_ctrl_csr_rw 2.440s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.480s 2.604ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.670s 4.669ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 3.290s 4.055ms 1 1 100.00
sysrst_ctrl_csr_rw 2.440s 2.069ms 1 1 100.00
sysrst_ctrl_csr_aliasing 3.480s 2.604ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.670s 4.669ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 11.020s 22.084ms 1 1 100.00
sysrst_ctrl_tl_intg_err 11.930s 22.419ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 11.930s 22.419ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 7.690s 14.168ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00