EDN Simulation Results

Wednesday March 12 2025 20:20:09 UTC

GitHub Revision: 0b3cc000b2

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.700s 41.131us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.450s 56.529us 1 1 100.00
V1 csr_rw edn_csr_rw 1.610s 44.355us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.270s 557.308us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.690s 94.833us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.630s 80.963us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.610s 44.355us 1 1 100.00
edn_csr_aliasing 1.690s 94.833us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.820s 48.651us 1 1 100.00
V2 csrng_commands edn_genbits 1.820s 48.651us 1 1 100.00
V2 genbits edn_genbits 1.820s 48.651us 1 1 100.00
V2 interrupts edn_intr 1.440s 28.451us 1 1 100.00
V2 alerts edn_alert 1.590s 72.611us 1 1 100.00
V2 errs edn_err 1.530s 33.571us 1 1 100.00
V2 disable edn_disable 1.500s 27.771us 1 1 100.00
edn_disable_auto_req_mode 1.520s 43.171us 1 1 100.00
V2 stress_all edn_stress_all 3.900s 768.811us 1 1 100.00
V2 intr_test edn_intr_test 1.460s 40.051us 1 1 100.00
V2 alert_test edn_alert_test 1.510s 49.398us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.700s 296.919us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.700s 296.919us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.450s 56.529us 1 1 100.00
edn_csr_rw 1.610s 44.355us 1 1 100.00
edn_csr_aliasing 1.690s 94.833us 1 1 100.00
edn_same_csr_outstanding 1.550s 80.703us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.450s 56.529us 1 1 100.00
edn_csr_rw 1.610s 44.355us 1 1 100.00
edn_csr_aliasing 1.690s 94.833us 1 1 100.00
edn_same_csr_outstanding 1.550s 80.703us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.160s 1.141ms 1 1 100.00
edn_tl_intg_err 2.060s 198.832us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.650s 50.011us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.590s 72.611us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.160s 1.141ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.160s 1.141ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.160s 1.141ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.160s 1.141ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.590s 72.611us 1 1 100.00
edn_sec_cm 4.160s 1.141ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.590s 72.611us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.060s 198.832us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets