CHIP Simulation Results

Wednesday March 12 2025 20:20:09 UTC

GitHub Revision: `0b3cc000b2`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.202m		0	1	0.00
		chip_sw_example_rom	1.058m	2.502ms	1	1	100.00
		chip_sw_example_manufacturer	1.872m	2.818ms	1	1	100.00
		chip_sw_example_concurrency	2.101m	2.874ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.891m	4.494ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.294m	4.043ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.999m	8.463ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	47.705m	31.903ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	42.580s	2.420ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	47.705m	31.903ms	1	1	100.00
		chip_csr_rw	2.294m	4.043ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.330s	185.153us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	2.319m	2.988ms	0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	2.319m	2.988ms	0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	2.319m	2.988ms	0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.917m	4.271ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.917m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.069m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.863m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.095m	4.271ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	25.240s	10.340us	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	25.660s	10.340us	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	24.080s	10.340us	0	1	0.00
V1		TOTAL			12	18	66.67
V2	chip_pin_mux	chip_padctrl_attributes	2.011m	4.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.011m	4.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.475m	3.138ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.636m	5.503ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.350m	3.742ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.535m	2.919ms	1	1	100.00
		chip_tap_straps_testunlock0	3.822m	5.475ms	1	1	100.00
		chip_tap_straps_rma	3.883m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.452m	2.919ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.972m	2.952ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.303m	8.692ms	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.738m	5.196ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.738m	5.196ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.478m	7.268ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	28.226m	19.282ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.785m	4.107ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.467m	5.931ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	48.062m	19.026ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.031m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.415m	6.115ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.027m	2.973ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.095m	9.443ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.351m	3.075ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.367m	4.390ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.793m	2.822ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.812m	3.124ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.687m	6.597ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.353m	5.240ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.928m	2.891ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.353m	5.240ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.862m	2.819ms	1	1	100.00
		chip_sw_aes_smoketest	2.059m	2.955ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.406m	3.088ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.928m	2.838ms	1	1	100.00
		chip_sw_csrng_smoketest	1.956m	2.844ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.785m	3.587ms	1	1	100.00
		chip_sw_gpio_smoketest	1.956m	2.888ms	0	1	0.00
		chip_sw_hmac_smoketest	2.666m	3.200ms	1	1	100.00
		chip_sw_kmac_smoketest	2.294m	3.036ms	1	1	100.00
		chip_sw_otbn_smoketest	13.101m	8.304ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.428m	5.487ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.415m	5.476ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.953m	2.850ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.024m	2.989ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.778m	2.820ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.853m	2.840ms	1	1	100.00
		chip_sw_uart_smoketest	2.000m	2.966ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.941m	2.862ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.259m	4.376ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.897h	60.365ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.516m	14.995ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.098m	5.249ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	5.028m	4.362ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.529m	10.143ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.714h	53.218ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.861h	55.938ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	41.150s	2.419ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	41.150s	2.419ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	47.705m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.392m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.891m	4.494ms	1	1	100.00
		chip_csr_rw	2.294m	4.043ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	47.705m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.392m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.891m	4.494ms	1	1	100.00
		chip_csr_rw	2.294m	4.043ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	46.100s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.700s	51.903us	1	1	100.00
		xbar_smoke_large_delays	43.330s	7.416ms	1	1	100.00
		xbar_smoke_slow_rsp	37.850s	4.510ms	1	1	100.00
		xbar_random_zero_delays	27.110s	587.063us	1	1	100.00
		xbar_random_large_delays	5.318m	54.598ms	1	1	100.00
		xbar_random_slow_rsp	4.648m	33.551ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	28.170s	1.309ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.190s	1.303ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	45.670s	2.371ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.190s	1.303ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	52.360s	2.200ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.963m	64.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.590s	1.063ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.139m	3.101ms	1	1	100.00
		xbar_stress_all_with_error	1.046m	3.101ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.099m	7.159ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.205m	7.159ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.516m	14.995ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.682m	25.756ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.255m	14.928ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.457m	11.207ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	36.928m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.188m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.053m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	36.964m	14.867ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	23.840s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.410s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.130s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.870s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	25.950s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.250s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	25.790s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	25.550s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.730s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.290s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.570s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.860s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.210s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.880s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.360s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.400s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.630s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.560s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	26.350s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.480s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.380s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.870s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.600s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.250s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	26.280s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.080m	11.215ms	1	1	100.00
		rom_e2e_asm_init_dev	36.854m	15.583ms	1	1	100.00
		rom_e2e_asm_init_prod	38.124m	15.582ms	1	1	100.00
		rom_e2e_asm_init_prod_end	35.569m	15.583ms	1	1	100.00
		rom_e2e_asm_init_rma	35.221m	14.883ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.733m	15.202ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.465m	15.166ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.241m	15.166ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.182m	15.875ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.221m	18.574ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.221m	18.574ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.153m	2.955ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.031m	2.974ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.010m	2.850ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.905m	2.830ms	0	1	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.276m	9.554ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.035m	2.965ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.135m	4.782ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.540m	5.344ms	1	1	100.00
		chip_plic_all_irqs_10	3.594m	3.624ms	1	1	100.00
		chip_plic_all_irqs_20	4.721m	4.266ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.508m	3.269ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.000m	11.255ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.938m	4.864ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.832m	2.815ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.434m	11.384ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.506m	7.933ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.329m	7.695ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	10.235m	7.953ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.975h	254.987ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.047m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.428m	5.487ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.047m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.513m	7.868ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.513m	7.868ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.588m	6.723ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.633m	4.859ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.309m	4.634ms	0	1	0.00
		chip_sw_aes_idle	1.905m	2.830ms	0	1	0.00
		chip_sw_hmac_enc_idle	1.861m	2.819ms	0	1	0.00
		chip_sw_kmac_idle	1.950m	2.843ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.443m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.477m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.261m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.512m	4.044ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.417m	9.288ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.083m	4.033ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.168m	4.651ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.157m	4.033ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.958m	4.651ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.482m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.896m	4.655ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.478m	7.268ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.789m	5.738ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.157m	4.033ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.958m	4.651ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.785m	4.107ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.467m	5.931ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	48.062m	19.026ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.031m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.415m	6.115ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.027m	2.973ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.095m	9.443ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.351m	3.075ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.367m	4.390ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.793m	2.822ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.706m	2.829ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.882m	4.665ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.181m	7.276ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	45.700m	25.266ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.881m	3.047ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.011m	3.046ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.477m	9.558ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.426m	3.191ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.225m	4.558ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	14.824m	18.289ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.535h	68.233ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.478m	7.268ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.500m	4.613ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.255m	3.423ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.506m	7.933ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.058m	6.622ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.015m	2.880ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.745m	5.675ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.966m	2.871ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	43.543m	17.550ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.875m	2.847ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.103m	6.061ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.875m	2.847ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.058m	6.622ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.950m	2.841ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.766m	17.486ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.187m	5.585ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.467m	5.931ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.177m	3.963ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.785m	4.107ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	46.255m	42.980ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.766m	17.486ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.866m	3.444ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.826m	9.417ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.813m	4.437ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	46.255m	42.980ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.813m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.813m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.813m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.813m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.668m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.341m	5.164ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.070m	4.936ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.070m	4.936ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.104m	2.954ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.027m	2.973ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.861m	2.819ms	0	1	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.594m	3.103ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	9.787m	6.257ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.285m	5.358ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.980m	5.358ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.782m	5.358ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.123m	4.078ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.826m	9.417ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.095m	9.443ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.398m	9.473ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.276m	9.554ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.028m	14.238ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.018m	2.874ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.458m	3.045ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.351m	3.075ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.826m	9.417ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.894m	2.833ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.367m	8.264ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.950m	2.843ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.135m	4.782ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.535m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.883m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.452m	2.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.034m	2.880ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.338m	9.417ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.813m	4.437ms	1	1	100.00
		chip_sw_flash_rma_unlocked	46.255m	42.980ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.627m	3.265ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.968m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.715m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.986m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.826m	9.417ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.713m	8.840ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.826m	7.135ms	1	1	100.00
		chip_prim_tl_access	1.668m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.789m	5.738ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.083m	4.033ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.168m	4.651ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.157m	4.033ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.958m	4.651ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.482m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.896m	4.655ms	1	1	100.00
		chip_tap_straps_dev	1.535m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.883m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.452m	2.919ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.809m	10.388ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.023m	3.459ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.267m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.290m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.226m	3.372ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.161m	23.466ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.809m	10.388ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	52.922m	47.185ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	52.508m	47.185ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.572m	8.110ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	54.169m	45.720ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	17.161m	23.466ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	58.800s	2.488ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.068m	2.532ms	1	1	100.00
		rom_volatile_raw_unlock	1.010m	2.532ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	49.375m	17.390ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	48.062m	19.026ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.309m	4.634ms	0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.309m	4.634ms	0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.309m	4.634ms	0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.039m	3.644ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.766m	17.486ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.039m	3.644ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.826m	9.417ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.250m	4.350ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.076m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.766m	17.486ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.039m	3.644ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.826m	9.417ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.250m	4.350ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.076m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.811m	4.514ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.034m	2.880ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.627m	3.265ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	6.968m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.715m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.986m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	4.073m	5.713ms	1	1	100.00
		chip_prim_tl_access	1.668m	4.853ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.668m	4.853ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	13.954m	8.578ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.759m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	11.680m	20.848ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.292m	7.381ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.301m	7.689ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.596m	5.879ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.048m	21.458ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.408m	13.249ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.513m	7.868ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.214m	10.154ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.353m	4.448ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.759m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.138m	4.037ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.902m	29.906ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.512m	6.182ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.472m	4.817ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.839m	20.500ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.173m	6.805ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.328m	9.734ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.891m	22.537ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.155m	3.089ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.713m	8.840ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.713m	8.840ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.328m	9.734ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.839m	20.500ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.353m	4.448ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.428m	5.487ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.228m	3.957ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.374m	4.042ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.326m	3.941ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.000m	11.255ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.878m	2.871ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.329m	7.695ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.606m	4.833ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.285m	4.815ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.362m	3.003ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.076m	2.899ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.374m	4.042ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.374m	4.042ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.420m	9.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.856m	13.888ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.228m	3.957ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.699m	4.258ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.523m	5.726ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.883m	5.475ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.809m	10.388ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.540m	5.344ms	1	1	100.00
		chip_plic_all_irqs_10	3.594m	3.624ms	1	1	100.00
		chip_plic_all_irqs_20	4.721m	4.266ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.982m	2.860ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.097m	2.989ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.516m	14.995ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.980m	6.770ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.717m	3.136ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.799m	3.342ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.263m	3.005ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.250m	4.350ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.367m	4.390ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.085m	7.067ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.306m	7.151ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.826m	7.135ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.738m	5.196ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.173m	6.805ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.521m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.108m	2.900ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.885m	3.615ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.171m	4.545ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.521m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.521m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.297m	11.578ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.297m	11.578ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.532m	5.613ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.221m	18.574ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.907m	2.843ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.934m	2.875ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.627m	3.657ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.329m	3.865ms	0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.110m	8.143ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.223h	31.559ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	24.559m	12.117ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.082m	2.903ms	1	1	100.00
V2		TOTAL			234	275	85.09
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.087m	2.945ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.877m	2.813ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.377h	71.600ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.946m	5.629ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.770m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.296m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.941m	11.323ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.659m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.564m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.539m	4.125ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.025s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.683m	5.153ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.031m	2.659ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.632m	4.364ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.777m	8.141ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.042m	2.203ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.650m	5.114ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	56.740s	2.427ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.832m	4.939ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.482m	5.531ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.717m	4.407ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.328m	9.734ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.770m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.296m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.941m	11.323ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.017s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.126m	4.935ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.378h	38.328ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.378h	38.328ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.212m	3.466ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.917m	4.271ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	41.821m	18.740ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.263m	3.006ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.819m	4.935ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.881m	2.864ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.489m	3.109ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.192m	3.853ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.018s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.362m	3.067ms	1	1	100.00
		TOTAL			274	325	84.31

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1
Line 524, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1
Line 499, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1
Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1
Line 497, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1
Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1
Line 484, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1
Line 509, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1
Line 504, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1
Line 484, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1
Line 507, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat" has 3 failures:
- Test chip_sw_uart_rand_baudrate has 1 failures.
  - 0.chip_sw_uart_rand_baudrate.1
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.1
    Line 403, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 3 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.106s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rv_dm_access_after_escalation_reset has 1 failures.

0.chip_sw_rv_dm_access_after_escalation_reset.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 1.585s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.119s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1
    Line 469, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1
    Line 474, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1
    Line 490, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1
    Line 507, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1
    Line 475, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1
    Line 522, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1
    Line 467, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Error: ProcessWrapperError("failed to spawn child process: Operation not permitted (os error *)") has 1 failures:

Test chip_sw_example_flash has 1 failures.

0.chip_sw_example_flash.1
Line 328, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

  Error: ProcessWrapperError("failed to spawn child process: Operation not permitted (os error 1)")
  Target //sw/device/tests:example_test_from_flash_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  INFO: Elapsed time: 62.261s, Critical Path: 3.94s
  INFO: 606 processes: 392 internal, 214 processwrapper-sandbox.

UVM_ERROR @ * us: (chip_sw_pwm_pulses_vseq.sv:55) virtual_sequencer [chip_sw_pwm_pulses_vseq] PWMCH* : lowpower counter is zero has 1 failures:
- Test chip_sw_sleep_pwm_pulses has 1 failures.
  - 0.chip_sw_sleep_pwm_pulses.1
    Line 459, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  UVM_ERROR @ 8692.474212 us: (chip_sw_pwm_pulses_vseq.sv:55) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_pwm_pulses_vseq] PWMCH0 : lowpower counter is zero
  UVM_INFO @ 8692.474212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_usbdev_setuprx has 1 failures.
  - 0.chip_sw_usbdev_setuprx.1
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest/run.log
```
  UVM_ERROR @ 3865.420540 us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 3865.420540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3136.260540 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3136.260540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = *, read = c) has 1 failures:
- Test chip_sw_gpio has 1 failures.
  - 0.chip_sw_gpio.1
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest/run.log
```
  UVM_ERROR @ 2987.560540 us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = 8, read = c)
  UVM_INFO @ 2987.560540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@102677) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4042.073916 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@102677) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4042.073916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.1
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11578.324124 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11578.324124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_randomness_test_sim_dv(sw/device/tests/otbn_randomness_test.c:127)] CHECK-fail: Clock enabled state is (*) and not as expected (*). has 1 failures:
- Test chip_sw_otbn_randomness has 1 failures.
  - 0.chip_sw_otbn_randomness.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest/run.log
```
  UVM_ERROR @ 4634.210540 us: (sw_logger_if.sv:526) [otbn_randomness_test_sim_dv(sw/device/tests/otbn_randomness_test.c:127)] CHECK-fail: Clock enabled state is (1) and not as expected (0).
  UVM_INFO @ 4634.210540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aes_idle_test_sim_dv(sw/device/tests/aes_idle_test.c:93)] CHECK-fail: Clock enabled state is (*) and not as expected (*). has 1 failures:
- Test chip_sw_aes_idle has 1 failures.
  - 0.chip_sw_aes_idle.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest/run.log
```
  UVM_ERROR @ 2830.130540 us: (sw_logger_if.sv:526) [aes_idle_test_sim_dv(sw/device/tests/aes_idle_test.c:93)] CHECK-fail: Clock enabled state is (1) and not as expected (0).
  UVM_INFO @ 2830.130540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2964.620540 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2964.620540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2814.560540 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2814.560540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:579) [chip_sw_entropy_src_fuse_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert otp_ctrl_fatal_check_error fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.1
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2880.082856 us: (cip_base_vseq.sv:579) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert otp_ctrl_fatal_check_error fired unexpectedly!
  UVM_INFO @ 2880.082856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_enc_idle_test_sim_dv(sw/device/tests/hmac_enc_idle_test.c:75)] CHECK-fail: Clock enabled state is (*) and not as expected (*). has 1 failures:
- Test chip_sw_hmac_enc_idle has 1 failures.
  - 0.chip_sw_hmac_enc_idle.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest/run.log
```
  UVM_ERROR @ 2818.560540 us: (sw_logger_if.sv:526) [hmac_enc_idle_test_sim_dv(sw/device/tests/hmac_enc_idle_test.c:75)] CHECK-fail: Clock enabled state is (1) and not as expected (0).
  UVM_INFO @ 2818.560540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2419.289116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h106e8  a_data: 'h65c994b0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18abe  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2419.289116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.1
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2813.345540 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2813.345540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:104) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.1
    Line 420, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 4361.720540 us: (chip_sw_power_idle_load_vseq.sv:104) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 4361.720540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:127) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1
    Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 10142.943668 us: (chip_sw_power_sleep_load_vseq.sv:127) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 10142.943668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.1
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19281.827733 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19281.827733 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1
    Line 457, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1
    Line 452, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_smoketest_sim_dv(sw/device/tests/gpio_smoketest.c:57)] CHECK-fail: * != fd7ff8f* has 1 failures:
- Test chip_sw_gpio_smoketest has 1 failures.
  - 0.chip_sw_gpio_smoketest.1
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest/run.log
```
  UVM_ERROR @ 2887.540540 us: (sw_logger_if.sv:526) [gpio_smoketest_sim_dv(sw/device/tests/gpio_smoketest.c:57)] CHECK-fail: 250fe8c6 != fd7ff8f6
  UVM_INFO @ 2887.540540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1
Line 237, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2420.279116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: 'h104fc  a_data: 'hb08d55f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a9be  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2420.279116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---