CHIP Simulation Results

Thursday March 13 2025 21:02:43 UTC

GitHub Revision: `8190c6886d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.808m	2.819ms	1	1	100.00
		chip_sw_example_rom	1.024m	2.524ms	1	1	100.00
		chip_sw_example_manufacturer	1.868m	2.819ms	1	1	100.00
		chip_sw_example_concurrency	2.125m	2.875ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.009m	4.494ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.353m	4.043ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.783m	8.463ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	46.586m	31.903ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	42.540s	2.420ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	46.586m	31.903ms	1	1	100.00
		chip_csr_rw	2.353m	4.043ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.820s	185.153us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	2.366m	3.001ms	0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	2.366m	3.001ms	0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	2.366m	3.001ms	0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.983m	4.271ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.983m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.444m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.635m	4.272ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.817m	4.272ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	24.800s	10.340us	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	24.620s	10.340us	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	24.900s	10.340us	0	1	0.00
V1		TOTAL			13	18	72.22
V2	chip_pin_mux	chip_padctrl_attributes	1.857m	4.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.857m	4.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.461m	3.138ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.219m	5.504ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.327m	3.742ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.448m	2.919ms	1	1	100.00
		chip_tap_straps_testunlock0	3.897m	5.475ms	1	1	100.00
		chip_tap_straps_rma	3.924m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.465m	2.919ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.959m	2.952ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.652m	8.693ms	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.019m	5.197ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.019m	5.197ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.678m	7.268ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	29.131m	19.282ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.732m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.179m	5.933ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	48.448m	18.979ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.198m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.467m	6.143ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.046m	2.974ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.918m	9.444ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.297m	3.075ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.437m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.805m	2.823ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.446m	3.125ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.820m	6.603ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.505m	5.231ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.977m	2.892ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.505m	5.231ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.825m	2.820ms	1	1	100.00
		chip_sw_aes_smoketest	2.127m	2.956ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.242m	3.093ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.900m	2.839ms	1	1	100.00
		chip_sw_csrng_smoketest	1.955m	2.845ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.825m	3.599ms	1	1	100.00
		chip_sw_gpio_smoketest	1.981m	2.891ms	0	1	0.00
		chip_sw_hmac_smoketest	2.607m	3.201ms	1	1	100.00
		chip_sw_kmac_smoketest	2.286m	3.036ms	1	1	100.00
		chip_sw_otbn_smoketest	14.043m	8.305ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.473m	5.487ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.397m	5.482ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.796m	2.851ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.049m	2.989ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.837m	2.821ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.876m	2.840ms	1	1	100.00
		chip_sw_uart_smoketest	2.064m	2.967ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.910m	2.863ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.231m	4.378ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.903h	60.358ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	36.946m	14.995ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.100m	5.249ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	5.350m	4.367ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.606m	10.148ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.786h	53.233ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.879h	55.960ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	38.020s	2.419ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	38.020s	2.419ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	46.586m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.730m	15.238ms	1	1	100.00
		chip_csr_hw_reset	2.009m	4.494ms	1	1	100.00
		chip_csr_rw	2.353m	4.043ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	46.586m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.730m	15.238ms	1	1	100.00
		chip_csr_hw_reset	2.009m	4.494ms	1	1	100.00
		chip_csr_rw	2.353m	4.043ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	48.800s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.520s	51.903us	1	1	100.00
		xbar_smoke_large_delays	43.040s	7.416ms	1	1	100.00
		xbar_smoke_slow_rsp	36.750s	4.510ms	1	1	100.00
		xbar_random_zero_delays	26.880s	587.063us	1	1	100.00
		xbar_random_large_delays	5.238m	54.598ms	1	1	100.00
		xbar_random_slow_rsp	4.575m	33.551ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.360s	1.309ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.150s	1.303ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	44.640s	2.371ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.150s	1.303ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	54.060s	2.200ms	1	1	100.00
		xbar_access_same_device_slow_rsp	9.049m	64.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.340s	1.063ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.070m	3.101ms	1	1	100.00
		xbar_stress_all_with_error	1.035m	3.101ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.073m	7.159ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.198m	7.159ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	36.946m	14.995ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.740m	25.756ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.714m	14.928ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.742m	11.207ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	38.481m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.182m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	37.940m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.063m	14.867ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	24.180s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.800s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.760s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.570s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	26.400s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	26.140s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	25.820s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.160s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.110s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.650s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.440s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.730s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.130s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.900s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	26.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.620s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	26.020s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.830s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.370s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.790s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.750s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.460s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.290s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.880s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	25.480s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.648m	11.215ms	1	1	100.00
		rom_e2e_asm_init_dev	36.389m	15.583ms	1	1	100.00
		rom_e2e_asm_init_prod	36.505m	15.582ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.105m	15.583ms	1	1	100.00
		rom_e2e_asm_init_rma	34.585m	14.883ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.461m	15.202ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.350m	15.166ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.813m	15.166ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.254m	15.875ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.232m	18.575ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.232m	18.575ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.078m	2.956ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.198m	2.974ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.941m	2.850ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.932m	2.831ms	0	1	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.433m	9.553ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.129m	2.966ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.168m	4.782ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.765m	5.346ms	1	1	100.00
		chip_plic_all_irqs_10	3.553m	3.625ms	1	1	100.00
		chip_plic_all_irqs_20	4.986m	4.268ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.377m	3.205ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.430m	11.255ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.728m	4.864ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.906m	2.815ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.806m	11.344ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.798m	7.933ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.084m	7.696ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	10.361m	7.954ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.981h	254.992ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.056m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.473m	5.487ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.056m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.477m	7.869ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.477m	7.869ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.554m	6.728ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.687m	4.859ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.054m	4.646ms	0	1	0.00
		chip_sw_aes_idle	1.932m	2.831ms	0	1	0.00
		chip_sw_hmac_enc_idle	1.842m	2.819ms	0	1	0.00
		chip_sw_kmac_idle	1.934m	2.845ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.402m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.212m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.181m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.351m	4.044ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.091m	9.294ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.202m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.750m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.956m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.871m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.000m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.987m	4.655ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.678m	7.268ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.216m	5.739ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.956m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.871m	4.655ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.732m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.179m	5.933ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	48.448m	18.979ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.198m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.467m	6.143ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.046m	2.974ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.918m	9.444ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.297m	3.075ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.437m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.805m	2.823ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.628m	2.830ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.082m	4.664ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.142m	7.278ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.041m	25.198ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.030m	3.048ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.033m	3.047ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.909m	9.559ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.294m	3.192ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.467m	4.559ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	14.950m	18.488ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.502h	68.251ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.678m	7.268ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.615m	4.613ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.275m	3.423ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.798m	7.933ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.379m	6.634ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.151m	2.881ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.080m	5.677ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.984m	2.871ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	42.820m	17.563ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.840m	2.847ms	1	1	100.00
		chip_sw_edn_entropy_reqs	9.010m	6.087ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.840m	2.847ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.379m	6.634ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.933m	2.842ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.850m	17.557ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.013m	5.587ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.179m	5.933ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.531m	3.962ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.732m	4.106ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	45.731m	43.040ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.850m	17.557ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.806m	3.444ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	16.118m	9.418ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.017m	4.437ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	45.731m	43.040ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.017m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.017m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.017m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.017m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.579m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.884m	5.166ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.081m	4.936ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.081m	4.936ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.058m	2.956ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.046m	2.974ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.842m	2.819ms	0	1	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.449m	3.103ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	10.319m	6.259ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.892m	5.358ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.951m	5.359ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.504m	5.358ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.922m	4.078ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	16.118m	9.418ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	13.918m	9.444ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.662m	9.473ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.433m	9.553ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.414m	14.243ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.940m	2.875ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.509m	3.046ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.297m	3.075ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	16.118m	9.418ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.903m	2.833ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	15.545m	8.264ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.934m	2.845ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.168m	4.782ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.448m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.924m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.465m	2.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.976m	2.881ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	16.262m	9.418ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.017m	4.437ms	1	1	100.00
		chip_sw_flash_rma_unlocked	45.731m	43.040ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.693m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.325m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.241m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.019m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.118m	9.418ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.589m	8.840ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.250m	7.136ms	1	1	100.00
		chip_prim_tl_access	1.579m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.216m	5.739ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.202m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.750m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	4.956m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.871m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.000m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.987m	4.655ms	1	1	100.00
		chip_tap_straps_dev	1.448m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.924m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.465m	2.919ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.719m	10.388ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.142m	3.459ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.256m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.198m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.192m	3.372ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	16.971m	23.472ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.719m	10.388ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	52.435m	47.196ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	52.661m	47.196ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.816m	8.115ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	49.864m	45.726ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	16.971m	23.472ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	57.670s	2.488ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.021m	2.532ms	1	1	100.00
		rom_volatile_raw_unlock	1.009m	2.532ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	49.230m	17.348ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	48.448m	18.979ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.054m	4.646ms	0	1	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.054m	4.646ms	0	1	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.054m	4.646ms	0	1	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.867m	3.644ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.850m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.867m	3.644ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.118m	9.418ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.351m	4.351ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.996m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.850m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.867m	3.644ms	1	1	100.00
		chip_sw_keymgr_key_derivation	16.118m	9.418ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.351m	4.351ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.996m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.944m	4.516ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.976m	2.881ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.693m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.325m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.241m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.019m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.807m	5.714ms	1	1	100.00
		chip_prim_tl_access	1.579m	4.853ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.579m	4.853ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	13.889m	8.578ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.804m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	11.331m	20.848ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.277m	7.381ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.105m	7.690ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.736m	5.879ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.893m	21.467ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.086m	13.250ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.477m	7.869ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.380m	10.155ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.239m	4.448ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.804m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.220m	4.038ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.398m	29.916ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.682m	6.182ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.591m	4.818ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.439m	20.501ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.765m	6.806ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.670m	9.739ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.535m	22.554ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.235m	3.089ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.589m	8.840ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.589m	8.840ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.670m	9.739ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	19.439m	20.501ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.239m	4.448ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.473m	5.487ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.336m	3.958ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.466m	4.042ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.213m	3.947ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.430m	11.255ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.873m	2.872ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	14.084m	7.696ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.701m	4.832ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.674m	4.827ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.190m	3.003ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.996m	2.899ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.466m	4.042ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.466m	4.042ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.456m	9.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.838m	13.888ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.336m	3.958ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.800m	4.258ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.831m	5.726ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.924m	5.475ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.719m	10.388ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.765m	5.346ms	1	1	100.00
		chip_plic_all_irqs_10	3.553m	3.625ms	1	1	100.00
		chip_plic_all_irqs_20	4.986m	4.268ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.957m	2.861ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.119m	2.989ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	36.946m	14.995ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.978m	6.780ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.777m	3.146ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.678m	3.343ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.432m	3.019ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.351m	4.351ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.437m	4.391ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.078m	7.067ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.332m	7.151ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.250m	7.136ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.019m	5.197ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.765m	6.806ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.365m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.989m	2.900ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.873m	3.615ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.417m	4.545ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.365m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.365m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	9.968m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	9.968m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.706m	5.614ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.232m	18.575ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.876m	2.855ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.061m	2.887ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.688m	3.667ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.652m	3.877ms	0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	14.648m	8.154ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.249h	31.807ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.354m	12.130ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.106m	2.914ms	1	1	100.00
V2		TOTAL			234	275	85.09
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.385m	2.945ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.843m	2.814ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.423h	71.597ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.864m	5.651ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.229m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.407m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.277m	11.323ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.450m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.670m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.448m	4.125ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.009s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.915m	5.154ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.283m	2.671ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.393m	4.376ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.350m	8.141ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	2.888m	2.215ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.685m	5.114ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	54.750s	2.427ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.712m	4.940ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.510m	5.535ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.775m	4.408ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.670m	9.739ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.229m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.407m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.277m	11.323ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.018s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.034m	4.935ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.373h	38.328ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.373h	38.328ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.215m	3.466ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.983m	4.271ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	42.936m	18.978ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.298m	3.007ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.823m	4.935ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.990m	2.864ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.616m	3.110ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.135m	3.853ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.019s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.436m	3.068ms	1	1	100.00
		TOTAL			275	325	84.62

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1
Line 507, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1
Line 518, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1
Line 483, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1
Line 496, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1
Line 498, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1
Line 486, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1
Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1
Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1
Line 486, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1
Line 503, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat" has 3 failures:
- Test chip_sw_uart_rand_baudrate has 1 failures.
  - 0.chip_sw_uart_rand_baudrate.1
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.1
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 3 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.127s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rv_dm_access_after_escalation_reset has 1 failures.

0.chip_sw_rv_dm_access_after_escalation_reset.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 0.103s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.131s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1
    Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1
    Line 490, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1
    Line 500, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1
    Line 513, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1
    Line 467, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1
    Line 526, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1
    Line 461, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_pwm_pulses_vseq.sv:55) virtual_sequencer [chip_sw_pwm_pulses_vseq] PWMCH* : lowpower counter is zero has 1 failures:
- Test chip_sw_sleep_pwm_pulses has 1 failures.
  - 0.chip_sw_sleep_pwm_pulses.1
    Line 470, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  UVM_ERROR @ 8692.651924 us: (chip_sw_pwm_pulses_vseq.sv:55) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_pwm_pulses_vseq] PWMCH0 : lowpower counter is zero
  UVM_INFO @ 8692.651924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_usbdev_setuprx has 1 failures.
  - 0.chip_sw_usbdev_setuprx.1
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest/run.log
```
  UVM_ERROR @ 3877.469500 us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 3877.469500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3145.659500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3145.659500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = *, read = *) has 1 failures:
- Test chip_sw_gpio has 1 failures.
  - 0.chip_sw_gpio.1
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest/run.log
```
  UVM_ERROR @ 3000.769500 us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = 2, read = 3)
  UVM_INFO @ 3000.769500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98397) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 436, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4042.081836 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98397) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4042.081836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.1
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11578.992460 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11578.992460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otbn_randomness_test_sim_dv(sw/device/tests/otbn_randomness_test.c:127)] CHECK-fail: Clock enabled state is (*) and not as expected (*). has 1 failures:
- Test chip_sw_otbn_randomness has 1 failures.
  - 0.chip_sw_otbn_randomness.1
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otbn_randomness/latest/run.log
```
  UVM_ERROR @ 4645.529500 us: (sw_logger_if.sv:526) [otbn_randomness_test_sim_dv(sw/device/tests/otbn_randomness_test.c:127)] CHECK-fail: Clock enabled state is (1) and not as expected (0).
  UVM_INFO @ 4645.529500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aes_idle_test_sim_dv(sw/device/tests/aes_idle_test.c:93)] CHECK-fail: Clock enabled state is (*) and not as expected (*). has 1 failures:
- Test chip_sw_aes_idle has 1 failures.
  - 0.chip_sw_aes_idle.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aes_idle/latest/run.log
```
  UVM_ERROR @ 2830.569500 us: (sw_logger_if.sv:526) [aes_idle_test_sim_dv(sw/device/tests/aes_idle_test.c:93)] CHECK-fail: Clock enabled state is (1) and not as expected (0).
  UVM_INFO @ 2830.569500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2965.809500 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 2965.809500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2815.169500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2815.169500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:579) [chip_sw_entropy_src_fuse_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert otp_ctrl_fatal_check_error fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.1
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2880.770345 us: (cip_base_vseq.sv:579) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert otp_ctrl_fatal_check_error fired unexpectedly!
  UVM_INFO @ 2880.770345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_enc_idle_test_sim_dv(sw/device/tests/hmac_enc_idle_test.c:75)] CHECK-fail: Clock enabled state is (*) and not as expected (*). has 1 failures:
- Test chip_sw_hmac_enc_idle has 1 failures.
  - 0.chip_sw_hmac_enc_idle.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_enc_idle/latest/run.log
```
  UVM_ERROR @ 2819.089500 us: (sw_logger_if.sv:526) [hmac_enc_idle_test_sim_dv(sw/device/tests/hmac_enc_idle_test.c:75)] CHECK-fail: Clock enabled state is (1) and not as expected (0).
  UVM_INFO @ 2819.089500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2419.289116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h106e8  a_data: 'h65c994b0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18abe  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2419.289116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.1
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2813.964500 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2813.964500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:104) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.1
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 4366.739500 us: (chip_sw_power_idle_load_vseq.sv:104) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 4366.739500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:127) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1
    Line 440, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 10147.872420 us: (chip_sw_power_sleep_load_vseq.sv:127) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 10147.872420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.1
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19281.577616 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19281.577616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1
    Line 482, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1
    Line 477, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_smoketest_sim_dv(sw/device/tests/gpio_smoketest.c:57)] CHECK-fail: * != *bc96bf* has 1 failures:
- Test chip_sw_gpio_smoketest has 1 failures.
  - 0.chip_sw_gpio_smoketest.1
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio_smoketest/latest/run.log
```
  UVM_ERROR @ 2890.689500 us: (sw_logger_if.sv:526) [gpio_smoketest_sim_dv(sw/device/tests/gpio_smoketest.c:57)] CHECK-fail: 9a44e59a != 8bc96bf0
  UVM_INFO @ 2890.689500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1
Line 237, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2420.279116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: 'h104fc  a_data: 'hb08d55f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a9be  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2420.279116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---