ADC_CTRL Simulation Results

Monday March 17 2025 20:35:47 UTC

GitHub Revision: `d5eebc5dad`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.780s	5.900ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.790s	983.793us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.670s	574.623us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	15.310s	26.650ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.320s	929.376us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.610s	497.122us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.670s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.320s	929.376us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	filters_polled	adc_ctrl_filters_polled	2.058m	326.507ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.075m	330.444ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.118m	324.779ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.066m	320.179ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.170m	343.342ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.507m	390.507ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.205m	339.714ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.620s	1.758ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.170s	4.575ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	12.900s	30.838ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	34.250s	78.778ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.630m	407.443ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.630s	545.456us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.490s	539.539us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.690s	498.206us	0	1	0.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.690s	498.206us	0	1	0.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.790s	983.793us	1	1	100.00
		adc_ctrl_csr_rw	1.670s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.320s	929.376us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.350s	1.894ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.790s	983.793us	1	1	100.00
		adc_ctrl_csr_rw	1.670s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.320s	929.376us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.350s	1.894ms	1	1	100.00
V2		TOTAL			14	16	87.50
V2S	tl_intg_err	adc_ctrl_sec_cm	3.130s	4.428ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.550s	4.548ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.550s	4.548ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	3.170s	4.166ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			21	25	84.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:297) [adc_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 2 failures:

Test adc_ctrl_tl_errors has 1 failures.

0.adc_ctrl_tl_errors.1
Line 150, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_tl_errors/latest/run.log

  UVM_ERROR @ 498205707 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0xf0f5ce98
  UVM_INFO @ 498205707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

0.adc_ctrl_csr_mem_rw_with_rand_reset.1
Line 154, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 497122365 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.adc_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x435bb690
  UVM_INFO @ 497122365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
- Test adc_ctrl_clock_gating has 1 failures.
  - 0.adc_ctrl_clock_gating.1
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 1758090787 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 1758090787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (adc_ctrl_scoreboard.sv:216) scoreboard [scoreboard] Access unexpected addr * has 1 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.1
    Line 165, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4166485053 ps: (adc_ctrl_scoreboard.sv:216) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x3ac0b6e8
  UVM_INFO @ 4166485053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```