RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday March 17 2025 20:35:47 UTC

GitHub Revision: d5eebc5dad

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.830s	2.553ms	1	1	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.740s	494.058us	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.690s	393.298us	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	9.400s	14.325ms	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.990s	897.819us	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	5.250s	7.081ms	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	4.230s	5.157ms	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	6.790s	9.587ms	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	43.520s	77.514ms	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.080s	1.090ms	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.860s	678.335us	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.720s	696.059us	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.840s	603.817us	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.860s	456.851us	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.410s	1.655ms	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.680s	286.229us	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.010s	1.030ms	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.080s	1.090ms	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.950s	480.437us	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.170s	933.888us	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.720s	696.059us	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.740s	135.469us	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.020s	301.849us	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	2.000s	227.849us	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	22.760s	8.519ms	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	20.980s	5.995ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	1.480s	79.400us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	20.980s	5.995ms	1	1	100.00
		rv_dm_csr_rw	2.000s	227.849us	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	1.350s	110.400us	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.370s	110.400us	1	1	100.00
V1		TOTAL			26	27	96.30
V2	idcode	rv_dm_smoke	2.830s	2.553ms	1	1	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.770s	697.025us	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.810s	537.230us	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.860s	470.161us	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.390s	1.599ms	1	1	100.00
V2	sba	rv_dm_sba_tl_access	7.580s	10.661ms	1	1	100.00
		rv_dm_delayed_resp_sba_tl_access	5.560s	7.116ms	1	1	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	7.740s	10.930ms	1	1	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	29.420s	49.333ms	1	1	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.840s	526.782us	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.510s	4.126ms	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.690s	661.300us	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.670s	272.056us	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	14.210s	19.335ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.600s	79.400us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.620s	278.711us	1	1	100.00
V2	stress_all	rv_dm_stress_all	2.320s	1.441ms	1	1	100.00
V2	alert_test	rv_dm_alert_test	1.430s	108.779us	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	1.600s	79.469us	0	1	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	1.600s	79.469us	0	1	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	20.980s	5.995ms	1	1	100.00
		rv_dm_csr_hw_reset	2.020s	301.849us	1	1	100.00
		rv_dm_csr_rw	2.000s	227.849us	1	1	100.00
		rv_dm_same_csr_outstanding	3.710s	733.990us	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	20.980s	5.995ms	1	1	100.00
		rv_dm_csr_hw_reset	2.020s	301.849us	1	1	100.00
		rv_dm_csr_rw	2.000s	227.849us	1	1	100.00
		rv_dm_same_csr_outstanding	3.710s	733.990us	1	1	100.00
V2		TOTAL			16	19	84.21
V2S	tl_intg_err	rv_dm_sec_cm	2.160s	1.114ms	1	1	100.00
		rv_dm_tl_intg_err	8.000s	3.216ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	8.000s	3.216ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.510s	4.126ms	1	1	100.00
		rv_dm_debug_disabled	1.750s	150.883us	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.510s	4.126ms	1	1	100.00
		rv_dm_debug_disabled	1.750s	150.883us	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	2.830s	2.553ms	1	1	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.840s	438.988us	0	1	0.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.610s	220.375us	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.610s	220.375us	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.840s	438.988us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.510s	79.365us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	1.540s	40.848us	1	1	100.00
		TOTAL			47	53	88.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:297) [rv_dm_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 3 failures:

  • Test rv_dm_tap_fsm_rand_reset has 1 failures.

    • 0.rv_dm_tap_fsm_rand_reset.1
      Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

        UVM_ERROR @  79399685 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x2d653f90
        UVM_INFO @  79399685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_tl_errors has 1 failures.

    • 0.rv_dm_tl_errors.1
      Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

        UVM_ERROR @  79468651 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x6ef5c540
        UVM_INFO @  79468651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rv_dm_csr_mem_rw_with_rand_reset.1
      Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  79399685 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x2d653f90
        UVM_INFO @  79399685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[NOA] Null object access has 1 failures:

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.1
      Line 89, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

        Error-[NOA] Null object access
        ../src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 303
          The object at dereference depth 0 is being used before it was
          constructed/allocated.
          Please make sure that the object is allocated before using it.
      

• UVM_ERROR (rv_dm_buffered_enable_vseq.sv:109) [rv_dm_buffered_enable_vseq] Check failed (seq.rsp.d_error == !(tgt_copy == Fetch)) has 1 failures:

  • Test rv_dm_buffered_enable has 1 failures.

    • 0.rv_dm_buffered_enable.1
      Line 83, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_buffered_enable/latest/run.log

        UVM_ERROR @ 438988409 ps: (rv_dm_buffered_enable_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.rv_dm_buffered_enable_vseq] Check failed (seq.rsp.d_error == !(tgt_copy == Fetch))
        UVM_INFO @ 438988409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_dm_scoreboard.sv:324) scoreboard [scoreboard] Access unexpected addr * has 1 failures:

  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 0.rv_dm_stress_all_with_rand_reset.1
      Line 74, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  79365202 ps: (rv_dm_scoreboard.sv:324) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x2d653f90
        UVM_INFO @  79365202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---