d5eebc5dad| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 2.350s | 2.140ms | 1 | 1 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 2.540s | 2.479ms | 1 | 1 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 2.380s | 2.188ms | 1 | 1 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 2.620s | 2.333ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 3.120s | 4.055ms | 1 | 1 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 2.200s | 2.069ms | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 19.020s | 38.935ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 3.450s | 2.604ms | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 2.350s | 2.002ms | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 2.200s | 2.069ms | 1 | 1 | 100.00 |
| sysrst_ctrl_csr_aliasing | 3.450s | 2.604ms | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 8 | 9 | 88.89 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 39.700s | 89.215ms | 1 | 1 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 55.390s | 124.363ms | 1 | 1 | 100.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 2.800s | 3.034ms | 1 | 1 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 31.930s | 1.116s | 1 | 1 | 100.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 2.640s | 2.538ms | 1 | 1 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 2.340s | 2.176ms | 1 | 1 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 3.570s | 4.403ms | 1 | 1 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 2.640s | 2.627ms | 1 | 1 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 2.480s | 5.148ms | 1 | 1 | 100.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 19.230s | 41.727ms | 1 | 1 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 6.270s | 12.161ms | 1 | 1 | 100.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 2.210s | 2.043ms | 1 | 1 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 2.450s | 2.034ms | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 2.350s | 2.011ms | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 2.350s | 2.011ms | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 3.120s | 4.055ms | 1 | 1 | 100.00 |
| sysrst_ctrl_csr_rw | 2.200s | 2.069ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 3.450s | 2.604ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 3.590s | 4.669ms | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 3.120s | 4.055ms | 1 | 1 | 100.00 |
| sysrst_ctrl_csr_rw | 2.200s | 2.069ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 3.450s | 2.604ms | 1 | 1 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 3.590s | 4.669ms | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 14 | 15 | 93.33 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 10.880s | 22.084ms | 1 | 1 | 100.00 |
| sysrst_ctrl_tl_intg_err | 11.520s | 22.419ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 11.520s | 22.419ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 2.250s | 2.002ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 24 | 27 | 88.89 |
UVM_ERROR (cip_base_vseq.sv:297) [sysrst_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 2 failures:
Test sysrst_ctrl_tl_errors has 1 failures.
0.sysrst_ctrl_tl_errors.1
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest/run.log
UVM_ERROR @ 2006217771 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x459fbe1c
UVM_FATAL @ 2011092810 ps: (sysrst_ctrl_scoreboard.sv:79) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x9cf5d83c
UVM_INFO @ 2011092810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2002134405 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x435bb690
UVM_ERROR @ 2002384407 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4cc959a4
UVM_INFO @ 2002384407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sysrst_ctrl_scoreboard.sv:79) scoreboard [scoreboard] Access unexpected addr * has 1 failures:
0.sysrst_ctrl_stress_all_with_rand_reset.1
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2002092738 ps: (sysrst_ctrl_scoreboard.sv:79) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x435bb690
UVM_INFO @ 2002092738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---