UART Simulation Results

Monday March 17 2025 20:35:47 UTC

GitHub Revision: d5eebc5dad

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.200s	554.831us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.480s	60.744us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.330s	49.994us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.570s	704.291us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.520s	96.494us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.520s	26.952us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.330s	49.994us	1	1	100.00
		uart_csr_aliasing	1.520s	96.494us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	base_random_seq	uart_tx_rx	19.890s	45.094ms	1	1	100.00
V2	parity	uart_smoke	2.200s	554.831us	1	1	100.00
		uart_tx_rx	19.890s	45.094ms	1	1	100.00
V2	parity_error	uart_intr	4.890s	14.778ms	1	1	100.00
		uart_rx_parity_err	13.670s	38.503ms	1	1	100.00
V2	watermark	uart_tx_rx	19.890s	45.094ms	1	1	100.00
		uart_intr	4.890s	14.778ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.973m	187.924ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	8.020s	24.375ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.640s	38.146ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.890s	14.778ms	1	1	100.00
V2	rx_break_err	uart_intr	4.890s	14.778ms	1	1	100.00
V2	rx_timeout	uart_intr	4.890s	14.778ms	1	1	100.00
V2	perf	uart_perf	1.986m	13.662ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.780s	5.722ms	1	1	100.00
V2	line_loopback	uart_loopback	6.780s	5.722ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	53.410s	156.430ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.340s	3.653ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.560s	2.731ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.970s	5.226ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.810m	99.004ms	1	1	100.00
V2	stress_all	uart_stress_all	7.086m	579.858ms	1	1	100.00
V2	alert_test	uart_alert_test	1.330s	49.077us	1	1	100.00
V2	intr_test	uart_intr_test	1.460s	47.702us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.460s	3.993us	0	1	0.00
V2	tl_d_illegal_access	uart_tl_errors	1.460s	3.993us	0	1	0.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.480s	60.744us	1	1	100.00
		uart_csr_rw	1.330s	49.994us	1	1	100.00
		uart_csr_aliasing	1.520s	96.494us	1	1	100.00
		uart_same_csr_outstanding	1.460s	84.702us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.480s	60.744us	1	1	100.00
		uart_csr_rw	1.330s	49.994us	1	1	100.00
		uart_csr_aliasing	1.520s	96.494us	1	1	100.00
		uart_same_csr_outstanding	1.460s	84.702us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.640s	252.120us	1	1	100.00
		uart_tl_intg_err	1.950s	335.413us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.950s	335.413us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.480s	3.827us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	27	88.89

Failure Buckets

• UVM_FATAL (uart_scoreboard.sv:171) scoreboard [scoreboard] Access unexpected addr * has 2 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.1
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   3826752 ps: (uart_scoreboard.sv:171) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x435bb690
        UVM_INFO @   3826752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test uart_tl_errors has 1 failures.

    • 0.uart_tl_errors.1
      Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_tl_errors/latest/run.log

        UVM_FATAL @   3993420 ps: (uart_scoreboard.sv:171) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xa4dd5c4
        UVM_INFO @   3993420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:297) [uart_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 1 failures:

  • Test uart_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.uart_csr_mem_rw_with_rand_reset.1
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   4035087 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x435bb690
        UVM_ERROR @   4326756 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4cc959a4
        UVM_ERROR @   4410090 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0xd63826e8
        UVM_ERROR @   7576782 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x597acf90
        UVM_ERROR @   8035119 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x597acf90