CHIP Simulation Results

Monday March 17 2025 20:35:47 UTC

GitHub Revision: `d5eebc5dad`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.369m		0	1	0.00
		chip_sw_example_rom	1.369m		0	1	0.00
		chip_sw_example_manufacturer	1.845m	2.819ms	1	1	100.00
		chip_sw_example_concurrency	2.122m	2.875ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.890m	4.494ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.481m	4.043ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	8.169m	8.463ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	50.858m	31.903ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	44.060s	2.420ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	50.858m	31.903ms	1	1	100.00
		chip_csr_rw	2.481m	4.043ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.010s	185.153us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	2.365m	3.001ms	0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	2.365m	3.001ms	0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	2.365m	3.001ms	0	1	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.580m	4.271ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.580m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.848m	4.271ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.143m	4.272ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.070m	4.272ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	24.640s	10.340us	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	25.240s	10.340us	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	24.440s	10.340us	0	1	0.00
V1		TOTAL			11	18	61.11
V2	chip_pin_mux	chip_padctrl_attributes	1.934m	4.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.934m	4.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.562m	3.138ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.708m	5.504ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.255m	3.742ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.450m	2.919ms	1	1	100.00
		chip_tap_straps_testunlock0	3.954m	5.475ms	1	1	100.00
		chip_tap_straps_rma	3.974m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.509m	2.919ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.161m	2.952ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.376m	8.693ms	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.124m	5.197ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.124m	5.197ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.250m	7.268ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	28.868m	19.282ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.910m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.481m	5.933ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.054m	18.979ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.245m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.521m	6.143ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.090m	2.974ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.500m	9.444ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.409m	3.075ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.555m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.758m	2.823ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.615m	3.125ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.983m	6.603ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.572m	5.231ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.147m	2.892ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.572m	5.231ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.916m	2.820ms	1	1	100.00
		chip_sw_aes_smoketest	2.194m	2.956ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.338m	3.093ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.920m	2.839ms	1	1	100.00
		chip_sw_csrng_smoketest	1.931m	2.845ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.962m	3.599ms	1	1	100.00
		chip_sw_gpio_smoketest	2.437m	3.073ms	1	1	100.00
		chip_sw_hmac_smoketest	2.697m	3.201ms	1	1	100.00
		chip_sw_kmac_smoketest	2.424m	3.036ms	1	1	100.00
		chip_sw_otbn_smoketest	13.885m	8.305ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.471m	5.487ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.538m	5.482ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.800m	2.851ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.059m	2.989ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.895m	2.821ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.909m	2.840ms	1	1	100.00
		chip_sw_uart_smoketest	2.046m	2.967ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.910m	2.863ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.265m	4.378ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.968h	60.358ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	36.891m	14.995ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.112m	5.249ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	5.328m	4.367ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.379m	10.148ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.785h	53.233ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.875h	55.960ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	41.760s	2.419ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	41.760s	2.419ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	50.858m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	14.717m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.890m	4.494ms	1	1	100.00
		chip_csr_rw	2.481m	4.043ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	50.858m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	14.717m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.890m	4.494ms	1	1	100.00
		chip_csr_rw	2.481m	4.043ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	48.600s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.490s	51.903us	1	1	100.00
		xbar_smoke_large_delays	42.930s	7.416ms	1	1	100.00
		xbar_smoke_slow_rsp	37.380s	4.510ms	1	1	100.00
		xbar_random_zero_delays	29.260s	587.063us	1	1	100.00
		xbar_random_large_delays	5.373m	54.598ms	1	1	100.00
		xbar_random_slow_rsp	4.719m	33.551ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	28.750s	1.309ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.080s	1.303ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	45.650s	2.371ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.080s	1.303ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	53.700s	2.200ms	1	1	100.00
		xbar_access_same_device_slow_rsp	9.106m	64.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	18.470s	1.063ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.151m	3.101ms	1	1	100.00
		xbar_stress_all_with_error	1.060m	3.101ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.335m	7.159ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.395m	7.159ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	36.891m	14.995ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.829m	25.756ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.112m	14.928ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.697m	11.207ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	38.066m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.774m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.708m	15.566ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.290m	14.867ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	24.750s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.760s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	25.680s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.220s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	25.120s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.550s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	25.370s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	26.080s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.700s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.230s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.680s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.720s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.450s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.650s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.890s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.380s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.320s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.480s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.470s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.860s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	25.560s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.810s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.010s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.410s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	25.790s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.018m	11.215ms	1	1	100.00
		rom_e2e_asm_init_dev	37.519m	15.583ms	1	1	100.00
		rom_e2e_asm_init_prod	37.144m	15.582ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.786m	15.583ms	1	1	100.00
		rom_e2e_asm_init_rma	36.597m	14.883ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.941m	15.202ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.172m	15.166ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	37.012m	15.166ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.544m	15.875ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.322m	18.575ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.322m	18.575ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.143m	2.956ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.245m	2.974ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.876m	2.850ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.992m	2.865ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.367m	9.553ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.263m	2.966ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.080m	4.782ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	6.851m	5.346ms	1	1	100.00
		chip_plic_all_irqs_10	3.775m	3.625ms	1	1	100.00
		chip_plic_all_irqs_20	5.071m	4.268ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.536m	3.205ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.483m	11.255ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.042m	4.864ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.871m	2.815ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	8.880m	11.344ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.475m	7.933ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.568m	7.696ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.389m	7.954ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.966h	254.992ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.166m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.471m	5.487ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.166m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.321m	7.869ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.321m	7.869ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.619m	6.728ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.470m	4.859ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.246m	6.000ms	1	1	100.00
		chip_sw_aes_idle	1.992m	2.865ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.303m	2.997ms	1	1	100.00
		chip_sw_kmac_idle	1.870m	2.845ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.436m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.316m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.564m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.412m	4.044ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.185m	9.294ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.308m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.032m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.150m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.011m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.109m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.749m	4.655ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.250m	7.268ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.942m	5.739ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.150m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.011m	4.655ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.910m	4.106ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.481m	5.933ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.054m	18.979ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.245m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.521m	6.143ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.090m	2.974ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.500m	9.444ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.409m	3.075ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.555m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.758m	2.823ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.633m	2.830ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.852m	4.664ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.496m	7.278ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.442m	25.198ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.909m	3.048ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.862m	3.047ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.600m	9.559ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.333m	3.192ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.148m	4.559ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.242m	18.488ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.550h	68.251ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.250m	7.268ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.006m	4.613ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.124m	3.423ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.475m	7.933ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.394m	6.634ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.126m	2.881ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.754m	5.677ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.962m	2.871ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	42.818m	17.563ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.979m	2.847ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.780m	6.087ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.979m	2.847ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.394m	6.634ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.914m	2.842ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	15.030m	17.557ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	7.878m	5.587ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.481m	5.933ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.965m	3.962ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.910m	4.106ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	48.441m	43.040ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	15.030m	17.557ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.719m	3.444ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.305m	9.418ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.635m	4.437ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	48.441m	43.040ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.635m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.635m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.635m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.635m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.558m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.665m	5.166ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.342m	4.936ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.342m	4.936ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.217m	2.956ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.090m	2.974ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.303m	2.997ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.595m	3.103ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	10.019m	6.259ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.850m	5.358ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.276m	5.359ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.078m	5.358ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.962m	4.078ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.305m	9.418ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.500m	9.444ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	15.755m	9.473ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.367m	9.553ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.967m	14.243ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.018m	2.875ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.455m	3.046ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.409m	3.075ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.305m	9.418ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.911m	2.833ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	15.306m	8.264ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.870m	2.845ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.080m	4.782ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.450m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.974m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.509m	2.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.105m	2.881ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	16.666m	9.418ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.635m	4.437ms	1	1	100.00
		chip_sw_flash_rma_unlocked	48.441m	43.040ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.665m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.680m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.236m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.913m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.305m	9.418ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.816m	8.840ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.997m	7.136ms	1	1	100.00
		chip_prim_tl_access	1.558m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.942m	5.739ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.308m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.032m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.150m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.011m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.109m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.749m	4.655ms	1	1	100.00
		chip_tap_straps_dev	1.450m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.974m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.509m	2.919ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.966m	10.388ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.114m	3.459ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.304m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.296m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.247m	3.372ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.820m	23.472ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.966m	10.388ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	56.059m	47.196ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	54.327m	47.196ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.651m	8.115ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	50.976m	45.726ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	17.820m	23.472ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.026m	2.488ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.100m	2.532ms	1	1	100.00
		rom_volatile_raw_unlock	1.006m	2.532ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	47.524m	17.348ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	50.054m	18.979ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.246m	6.000ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.246m	6.000ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.246m	6.000ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.153m	3.644ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	15.030m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.153m	3.644ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.305m	9.418ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.436m	4.351ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.025m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	15.030m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.153m	3.644ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.305m	9.418ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.436m	4.351ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.025m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.835m	4.516ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.105m	2.881ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.665m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.680m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.236m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.913m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.928m	5.714ms	1	1	100.00
		chip_prim_tl_access	1.558m	4.853ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.558m	4.853ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	14.901m	8.578ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.026m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.187m	20.848ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.302m	7.381ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.335m	7.690ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.732m	5.879ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.977m	21.467ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.798m	13.250ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.321m	7.869ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.254m	10.155ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.415m	4.448ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.026m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.349m	4.038ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.267m	29.916ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.818m	6.182ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.480m	4.818ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.767m	20.501ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.323m	6.806ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.754m	9.739ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.062m	22.554ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.115m	3.089ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.816m	8.840ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.816m	8.840ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.754m	9.739ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.767m	20.501ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.415m	4.448ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.471m	5.487ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.202m	3.958ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.312m	4.042ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.253m	3.947ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.483m	11.255ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.041m	2.872ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.568m	7.696ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.518m	4.832ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.588m	4.827ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.194m	3.003ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.025m	2.899ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.312m	4.042ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.312m	4.042ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.752m	9.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.887m	13.888ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.202m	3.958ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.731m	4.258ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.611m	5.726ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.974m	5.475ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.966m	10.388ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	6.851m	5.346ms	1	1	100.00
		chip_plic_all_irqs_10	3.775m	3.625ms	1	1	100.00
		chip_plic_all_irqs_20	5.071m	4.268ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.927m	2.861ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.046m	2.989ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	36.891m	14.995ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.991m	6.780ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.642m	3.146ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.650m	3.343ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.488m	3.019ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.436m	4.351ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.555m	4.391ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.037m	7.067ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.641m	7.151ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.997m	7.136ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.124m	5.197ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.323m	6.806ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.118m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.001m	2.900ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.871m	3.615ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.619m	4.545ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.118m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.118m	22.557ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	9.873m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	9.873m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.713m	5.614ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.322m	18.575ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.973m	2.855ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.084m	2.887ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.959m	3.667ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.553m	3.877ms	0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	14.368m	8.154ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.254h	31.807ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	26.747m	12.130ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.026m	2.914ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.279m	2.945ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.969m	2.814ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.378h	71.597ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.517m	5.651ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.027m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.059m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.953m	11.323ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.619m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.615m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.694m	4.125ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.012s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.317m	5.154ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.078m	2.671ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.911m	4.376ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	15.171m	8.141ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	2.946m	2.215ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.013m	5.114ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	58.640s	2.427ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.797m	4.940ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.732m	5.535ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.578m	4.408ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.754m	9.739ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.027m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.059m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.953m	11.323ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.017s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.102m	4.935ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.352h	38.328ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.352h	38.328ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.246m	3.466ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.580m	4.271ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	41.825m	18.978ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.061m	3.007ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.160m	4.935ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.901m	2.864ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.564m	3.110ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.000m	3.853ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.025s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.330m	3.068ms	1	1	100.00
		TOTAL			277	325	85.23

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1
Line 489, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1
Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1
Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1
Line 499, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1
Line 487, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1
Line 486, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1
Line 486, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1
Line 486, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1
Line 508, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1
Line 514, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job returned non-zero exit code has 4 failures:

Test chip_sw_example_flash has 1 failures.

0.chip_sw_example_flash.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

  Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging
  src/main/tools/process-wrapper-legacy.cc:66: "fork": Resource temporarily unavailable
  [604 / 1,348] checking cached actions
  Target //sw/device/tests:example_test_from_flash_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  INFO: Elapsed time: 67.572s, Critical Path: 3.64s
  INFO: 604 processes: 391 internal, 213 processwrapper-sandbox.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.106s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rv_dm_access_after_escalation_reset has 1 failures.

0.chip_sw_rv_dm_access_after_escalation_reset.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 0.100s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.122s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat" has 3 failures:
- Test chip_sw_uart_rand_baudrate has 1 failures.
  - 0.chip_sw_uart_rand_baudrate.1
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1
    Line 505, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1
    Line 499, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1
    Line 528, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_vseq.sv:297) [chip_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 2 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2419.289116 us: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x000106e8
  UVM_INFO @ 2419.289116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1
Line 237, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2419.509116 us: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x40420054
  UVM_INFO @ 2419.509116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1
    Line 516, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1
    Line 477, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1
    Line 527, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1
    Line 460, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Error: ProcessWrapperError("failed to spawn child process: Operation not permitted (os error *)") has 1 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.1
Line 236, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Error: ProcessWrapperError("failed to spawn child process: Operation not permitted (os error 1)")
  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  INFO: Elapsed time: 68.808s, Critical Path: 0.52s
  INFO: 164 processes: 99 action cache hit, 107 internal, 57 processwrapper-sandbox.

UVM_ERROR @ * us: (chip_sw_pwm_pulses_vseq.sv:55) virtual_sequencer [chip_sw_pwm_pulses_vseq] PWMCH* : lowpower counter is zero has 1 failures:
- Test chip_sw_sleep_pwm_pulses has 1 failures.
  - 0.chip_sw_sleep_pwm_pulses.1
    Line 474, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  UVM_ERROR @ 8692.651924 us: (chip_sw_pwm_pulses_vseq.sv:55) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_pwm_pulses_vseq] PWMCH0 : lowpower counter is zero
  UVM_INFO @ 8692.651924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_usbdev_setuprx has 1 failures.
  - 0.chip_sw_usbdev_setuprx.1
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest/run.log
```
  UVM_ERROR @ 3877.469500 us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 3877.469500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3145.659500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3145.659500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = *, read = *) has 1 failures:
- Test chip_sw_gpio has 1 failures.
  - 0.chip_sw_gpio.1
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_gpio/latest/run.log
```
  UVM_ERROR @ 3000.769500 us: (sw_logger_if.sv:526) [gpio_test_sim_dv(sw/device/tests/sim_dv/gpio_test.c:89)] CHECK-fail: GPIOs mismatched (written = 2, read = 3)
  UVM_INFO @ 3000.769500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98397) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4042.081836 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98397) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4042.081836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.1
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11578.992460 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11578.992460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2965.809500 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 2965.809500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2815.169500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2815.169500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:579) [chip_sw_entropy_src_fuse_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert otp_ctrl_fatal_check_error fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.1
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2880.770345 us: (cip_base_vseq.sv:579) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert otp_ctrl_fatal_check_error fired unexpectedly!
  UVM_INFO @ 2880.770345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.1
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2813.964500 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2813.964500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:104) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.1
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 4366.739500 us: (chip_sw_power_idle_load_vseq.sv:104) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 4366.739500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:127) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1
    Line 444, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 10147.872420 us: (chip_sw_power_sleep_load_vseq.sv:127) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 10147.872420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.1
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19281.577616 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19281.577616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1
    Line 473, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1
    Line 491, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```