EDN Simulation Results

Tuesday March 18 2025 18:41:58 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.550s	41.131us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.700s	56.529us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.680s	44.355us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.290s	557.308us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.690s	94.833us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.400s	4.703us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.680s	44.355us	1	1	100.00
		edn_csr_aliasing	1.690s	94.833us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	firmware	edn_genbits	1.620s	48.651us	1	1	100.00
V2	csrng_commands	edn_genbits	1.620s	48.651us	1	1	100.00
V2	genbits	edn_genbits	1.620s	48.651us	1	1	100.00
V2	interrupts	edn_intr	1.680s	28.451us	1	1	100.00
V2	alerts	edn_alert	1.740s	72.611us	1	1	100.00
V2	errs	edn_err	1.600s	33.571us	1	1	100.00
V2	disable	edn_disable	1.450s	27.771us	1	1	100.00
		edn_disable_auto_req_mode	1.530s	43.171us	1	1	100.00
V2	stress_all	edn_stress_all	4.040s	768.811us	1	1	100.00
V2	intr_test	edn_intr_test	1.390s	40.051us	1	1	100.00
V2	alert_test	edn_alert_test	1.510s	49.398us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.530s	8.486us	0	1	0.00
V2	tl_d_illegal_access	edn_tl_errors	1.530s	8.486us	0	1	0.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.700s	56.529us	1	1	100.00
		edn_csr_rw	1.680s	44.355us	1	1	100.00
		edn_csr_aliasing	1.690s	94.833us	1	1	100.00
		edn_same_csr_outstanding	1.640s	80.703us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.700s	56.529us	1	1	100.00
		edn_csr_rw	1.680s	44.355us	1	1	100.00
		edn_csr_aliasing	1.690s	94.833us	1	1	100.00
		edn_same_csr_outstanding	1.640s	80.703us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	tl_intg_err	edn_sec_cm	4.170s	1.141ms	1	1	100.00
		edn_tl_intg_err	1.970s	198.832us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.570s	50.011us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.740s	72.611us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.170s	1.141ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.170s	1.141ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.170s	1.141ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.170s	1.141ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.740s	72.611us	1	1	100.00
		edn_sec_cm	4.170s	1.141ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.740s	72.611us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.970s	198.832us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.420s	4.011us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			18	21	85.71

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:297) [edn_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 3 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.1
      Line 99, in log /nightly/runs/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   4011206 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x7f9b82ac
        UVM_INFO @   4011206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_tl_errors has 1 failures.

    • 0.edn_tl_errors.1
      Line 79, in log /nightly/runs/scratch/master/edn-sim-vcs/0.edn_tl_errors/latest/run.log

        UVM_ERROR @   8485557 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x7f9b82c4
        UVM_INFO @   8485557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.edn_csr_mem_rw_with_rand_reset.1
      Line 80, in log /nightly/runs/scratch/master/edn-sim-vcs/0.edn_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   4702971 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x7f9b82ac
        UVM_INFO @   4702971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---