RV_TIMER Simulation Results

Tuesday March 18 2025 18:41:58 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.992m	345.317ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.490s	50.119us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.430s	44.994us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.700s	767.166us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.520s	95.952us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.360s	6.868us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.430s	44.994us	1	1	100.00
		rv_timer_csr_aliasing	1.520s	95.952us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	random_reset	rv_timer_random_reset	1.440s	38.869us	1	1	100.00
V2	disabled	rv_timer_disabled	1.357m	320.831ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.080s	17.912ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.080s	17.912ms	1	1	100.00
V2	stress	rv_timer_stress_all	8.985m	1.432s	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.480s	40.660us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.500s	8.077us	0	1	0.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.500s	8.077us	0	1	0.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.490s	50.119us	1	1	100.00
		rv_timer_csr_rw	1.430s	44.994us	1	1	100.00
		rv_timer_csr_aliasing	1.520s	95.952us	1	1	100.00
		rv_timer_same_csr_outstanding	1.570s	91.494us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.490s	50.119us	1	1	100.00
		rv_timer_csr_rw	1.430s	44.994us	1	1	100.00
		rv_timer_csr_aliasing	1.520s	95.952us	1	1	100.00
		rv_timer_same_csr_outstanding	1.570s	91.494us	1	1	100.00
V2		TOTAL			6	7	85.71
V2S	tl_intg_err	rv_timer_sec_cm	1.690s	254.662us	1	1	100.00
		rv_timer_tl_intg_err	1.820s	302.537us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.820s	302.537us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.360s	4.993us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			13	16	81.25

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:297) [rv_timer_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 3 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.1
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   4993428 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4deeb118
        UVM_INFO @   4993428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_tl_errors has 1 failures.

    • 0.rv_timer_tl_errors.1
      Line 70, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest/run.log

        UVM_ERROR @   8076786 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4deeb10c
        UVM_INFO @   8076786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.rv_timer_csr_mem_rw_with_rand_reset.1
      Line 71, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   6868443 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4deeb118
        UVM_INFO @   6868443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---