ENTROPY_SRC Simulation Results

Wednesday March 19 2025 18:38:49 UTC

GitHub Revision: cf25bf2795

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 5.000s 65.188us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 130.341us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 103.841us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 8.000s 1.962ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 729.691us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 5.591us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 103.841us 1 1 100.00
entropy_src_csr_aliasing 6.000s 729.691us 1 1 100.00
V1 TOTAL 5 6 83.33
V2 firmware entropy_src_smoke 5.000s 65.188us 1 1 100.00
entropy_src_rng 5.000s 12.302us 0 1 0.00
entropy_src_fw_ov 5.000s 6.847us 0 1 0.00
V2 firmware_mode entropy_src_fw_ov 5.000s 6.847us 0 1 0.00
V2 rng_mode entropy_src_rng 5.000s 12.302us 0 1 0.00
V2 rng_max_rate entropy_src_rng_max_rate 5.000s 6.282us 0 1 0.00
V2 health_checks entropy_src_rng 5.000s 12.302us 0 1 0.00
V2 conditioning entropy_src_rng 5.000s 12.302us 0 1 0.00
V2 interrupts entropy_src_rng 5.000s 12.302us 0 1 0.00
entropy_src_intr 6.000s 140.937us 1 1 100.00
V2 alerts entropy_src_rng 5.000s 12.302us 0 1 0.00
entropy_src_functional_alerts 6.000s 135.551us 1 1 100.00
V2 stress_all entropy_src_stress_all 2.017m 18.316ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 57.000s 10.039ms 0 1 0.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 6.000s 105.437us 1 1 100.00
V2 intr_test entropy_src_intr_test 5.000s 86.591us 1 1 100.00
V2 alert_test entropy_src_alert_test 5.000s 71.241us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 4.000s 5.491us 0 1 0.00
V2 tl_d_illegal_access entropy_src_tl_errors 4.000s 5.491us 0 1 0.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 130.341us 1 1 100.00
entropy_src_csr_rw 4.000s 103.841us 1 1 100.00
entropy_src_csr_aliasing 6.000s 729.691us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 222.891us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 130.341us 1 1 100.00
entropy_src_csr_rw 4.000s 103.841us 1 1 100.00
entropy_src_csr_aliasing 6.000s 729.691us 1 1 100.00
entropy_src_same_csr_outstanding 5.000s 222.891us 1 1 100.00
V2 TOTAL 7 12 58.33
V2S tl_intg_err entropy_src_sec_cm 5.000s 194.041us 1 1 100.00
entropy_src_tl_intg_err 6.000s 526.241us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 5.000s 12.302us 0 1 0.00
entropy_src_cfg_regwen 5.000s 76.691us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 5.000s 12.302us 0 1 0.00
V2S sec_cm_config_redun entropy_src_rng 5.000s 12.302us 0 1 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 5.000s 12.302us 0 1 0.00
entropy_src_fw_ov 5.000s 6.847us 0 1 0.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 57.000s 10.039ms 0 1 0.00
entropy_src_sec_cm 5.000s 194.041us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 57.000s 10.039ms 0 1 0.00
entropy_src_sec_cm 5.000s 194.041us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 5.000s 12.302us 0 1 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 57.000s 10.039ms 0 1 0.00
entropy_src_sec_cm 5.000s 194.041us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 57.000s 10.039ms 0 1 0.00
entropy_src_sec_cm 5.000s 194.041us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 57.000s 10.039ms 0 1 0.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 135.551us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 526.241us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.000s 12.302us 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 15 22 68.18

Failure Buckets