OTBN Simulation Results

Wednesday March 19 2025 18:38:49 UTC

GitHub Revision: cf25bf2795

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	181.441us	1	1	100.00
V1	single_binary	otbn_single	8.000s	42.641us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	46.791us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	52.041us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	245.841us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	5.941us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
V1	mem_walk	otbn_mem_walk	18.000s	3.013ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	11.000s	896.391us	1	1	100.00
V1		TOTAL			8	9	88.89
V2	reset_recovery	otbn_reset	16.000s	281.191us	1	1	100.00
V2	multi_error	otbn_multi_err	37.000s	781.091us	1	1	100.00
V2	back_to_back	otbn_multi	27.000s	415.091us	1	1	100.00
V2	stress_all	otbn_stress_all	23.000s	395.291us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	96.821us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	48.441us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	9.000s	50.191us	1	1	100.00
V2	alert_test	otbn_alert_test	8.000s	40.391us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	43.191us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	5.191us	0	1	0.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	5.191us	0	1	0.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	46.791us	1	1	100.00
		otbn_csr_rw	7.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	59.541us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	46.791us	1	1	100.00
		otbn_csr_rw	7.000s	52.041us	1	1	100.00
		otbn_csr_aliasing	7.000s	65.191us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	59.541us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	272.773us	1	1	100.00
		otbn_controller_ispr_rdata_err	10.000s	270.891us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	228.391us	0	1	0.00
		otbn_urnd_err	8.000s	29.202us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	42.583us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	30.012us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
		otbn_tl_intg_err	12.000s	294.191us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	470.491us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	181.441us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	81.916us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	81.154us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	12.000s	294.191us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	96.821us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	96.821us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	81.154us	1	1	100.00
		otbn_dmem_err	9.000s	81.916us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	48.441us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	28.964us	1	1	100.00
		otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	43.821us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	42.393us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	11.000s	143.078us	0	1	0.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	11.000s	143.078us	0	1	0.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	85.250us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	271.535us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	42.691us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	42.691us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	29.774us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	27.000s	415.091us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	43.041us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	8.000s	42.641us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.467m	2.644ms	1	1	100.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.000s	5.941us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			36	41	87.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:298) [otbn_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 3 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.1
      Line 142, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   5940573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x95c90008
        UVM_INFO @   5940573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_tl_errors has 1 failures.

    • 0.otbn_tl_errors.1
      Line 81, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_tl_errors/latest/run.log

        UVM_ERROR @   5190573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x95c90020
        UVM_INFO @   5190573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otbn_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.otbn_csr_mem_rw_with_rand_reset.1
      Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   5940573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x95c90008
        UVM_INFO @   5940573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal has unexpected timeout error has 1 failures:

  • Test otbn_mac_bignum_acc_err has 1 failures.

    • 0.otbn_mac_bignum_acc_err.1
      Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mac_bignum_acc_err/latest/run.log

        UVM_ERROR @ 228390574 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal has unexpected timeout error
        UVM_INFO @ 228390574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test otbn_rnd_sec_cm has 1 failures.

    • 0.otbn_rnd_sec_cm.1
      Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_rnd_sec_cm/latest/run.log

        UVM_FATAL @ 143077997 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 143077997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---