cf25bf2795| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 4.000s | 169.441us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 63.591us | 1 | 1 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 40.791us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 705.491us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 81.291us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 97.441us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 40.791us | 1 | 1 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 81.291us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | perf | pattgen_perf | 11.000s | 6.617ms | 1 | 1 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 11.000s | 6.602ms | 1 | 1 | 100.00 |
| V2 | error | pattgen_error | 4.000s | 125.191us | 1 | 1 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 4.000s | 185.941us | 1 | 1 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 4.000s | 42.891us | 1 | 1 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 56.141us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 3.000s | 15.141us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 3.000s | 15.141us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 63.591us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 3.000s | 40.791us | 1 | 1 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 81.291us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 4.000s | 96.191us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 63.591us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 3.000s | 40.791us | 1 | 1 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 81.291us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 4.000s | 96.191us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 209.441us | 1 | 1 | 100.00 |
| pattgen_sec_cm | 3.000s | 155.441us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 209.441us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 4.000s | 7.541us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.000s | 163.591us | 1 | 1 | 100.00 | |
| TOTAL | 15 | 18 | 83.33 |
UVM_ERROR (cip_base_vseq.sv:298) [pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 3 failures:
Test pattgen_tl_errors has 1 failures.
0.pattgen_tl_errors.1
Line 97, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_tl_errors/latest/run.log
UVM_ERROR @ 7290573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ed4
UVM_ERROR @ 8440573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ed4
UVM_FATAL @ 15140573 ps: (pattgen_scoreboard.sv:108) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
access unexpected addr 0xd77c4a4c
UVM_INFO @ 15140573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test pattgen_stress_all_with_rand_reset has 1 failures.
0.pattgen_stress_all_with_rand_reset.1
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4340573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ecc
UVM_ERROR @ 5290573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81edc
UVM_ERROR @ 5990573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ec8
UVM_FATAL @ 7540573 ps: (pattgen_scoreboard.sv:108) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
access unexpected addr 0x9e9c2e2c
Test pattgen_csr_mem_rw_with_rand_reset has 1 failures.
0.pattgen_csr_mem_rw_with_rand_reset.1
Line 98, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 4340573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ecc
UVM_ERROR @ 8940573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81edc
UVM_ERROR @ 13990573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ec8
UVM_ERROR @ 15990573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x9e9c2e2c
UVM_ERROR @ 17140573 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x15e81ee0