PWM Simulation Results

Thursday March 20 2025 20:21:30 UTC

GitHub Revision: 0164fe98ff

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	2.548ms	1	1	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	70.091us	1	1	100.00
V1	csr_rw	pwm_csr_rw	3.000s	55.341us	1	1	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	6.000s	1.223ms	1	1	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	205.341us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	94.891us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	55.341us	1	1	100.00
		pwm_csr_aliasing	4.000s	205.341us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	dutycycle	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	pulse	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	blink	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	heartbeat	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	resolution	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	multi_channel	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	polarity	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	phase	pwm_rand_output	37.000s	52.510ms	1	1	100.00
		pwm_phase	36.000s	52.513ms	1	1	100.00
V2	lowpower	pwm_rand_output	37.000s	52.510ms	1	1	100.00
V2	perf	pwm_perf	35.000s	52.901ms	1	1	100.00
V2	regwen	pwm_regwen	2.550m	52.495ms	1	1	100.00
V2	stress_all	pwm_stress_all	5.000s	2.530ms	0	1	0.00
V2	alert_test	pwm_alert_test	3.000s	43.941us	1	1	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	4.000s	306.041us	1	1	100.00
V2	tl_d_illegal_access	pwm_tl_errors	4.000s	306.041us	1	1	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	70.091us	1	1	100.00
		pwm_csr_rw	3.000s	55.341us	1	1	100.00
		pwm_csr_aliasing	4.000s	205.341us	1	1	100.00
		pwm_same_csr_outstanding	3.000s	143.441us	1	1	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	70.091us	1	1	100.00
		pwm_csr_rw	3.000s	55.341us	1	1	100.00
		pwm_csr_aliasing	4.000s	205.341us	1	1	100.00
		pwm_same_csr_outstanding	3.000s	143.441us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pwm_tl_intg_err	4.000s	291.291us	1	1	100.00
		pwm_sec_cm	3.000s	166.291us	1	1	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	4.000s	291.291us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	36.000s	52.494ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	17	94.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:452) [pwm_common_vseq] Check failed (intr_csrs.size() > *) Called intr_test vseq without any interrupt register. has 1 failures:
  • Test pwm_stress_all has 1 failures.

    • 0.pwm_stress_all.1
      Line 82, in log /nightly/runs/scratch/master/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log

        UVM_ERROR @ 2529540574 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 2529540574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---