CHIP Simulation Results

Thursday March 20 2025 20:21:30 UTC

GitHub Revision: `0164fe98ff`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.908m	2.819ms	1	1	100.00
		chip_sw_example_rom	1.045m	2.524ms	1	1	100.00
		chip_sw_example_manufacturer	1.763m	2.819ms	1	1	100.00
		chip_sw_example_concurrency	1.966m	2.874ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.943m	4.494ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.393m	4.043ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	8.130m	8.463ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	50.797m	31.903ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	43.510s	2.420ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	50.797m	31.903ms	1	1	100.00
		chip_csr_rw	2.393m	4.043ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.780s	185.153us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.698m	4.214ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.698m	4.214ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.698m	4.214ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.907m	4.272ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.907m	4.272ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.784m	4.272ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.627m	4.272ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.082m	4.272ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	25.700s	10.340us	0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	25.490s	10.340us	0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	25.100s	10.340us	0	1	0.00
V1		TOTAL			14	18	77.78
V2	chip_pin_mux	chip_padctrl_attributes	1.873m	4.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.873m	4.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.390m	3.138ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.327m	5.503ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.337m	3.737ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.441m	2.919ms	1	1	100.00
		chip_tap_straps_testunlock0	3.722m	5.475ms	1	1	100.00
		chip_tap_straps_rma	3.849m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.502m	2.919ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.033m	2.953ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.537m	8.693ms	0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.892m	5.209ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.892m	5.209ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.856m	7.273ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	30.424m	19.266ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.700m	4.100ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	7.941m	5.930ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	49.951m	18.978ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.022m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.588m	6.144ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.191m	2.973ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.616m	9.442ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.197m	3.083ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.205m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.768m	2.823ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.355m	3.122ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.538m	6.596ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.345m	5.231ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.951m	2.893ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.345m	5.231ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.891m	2.820ms	1	1	100.00
		chip_sw_aes_smoketest	2.225m	2.956ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.238m	3.088ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.760m	2.839ms	1	1	100.00
		chip_sw_csrng_smoketest	1.866m	2.844ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.748m	3.598ms	1	1	100.00
		chip_sw_gpio_smoketest	2.484m	3.074ms	1	1	100.00
		chip_sw_hmac_smoketest	2.703m	3.200ms	1	1	100.00
		chip_sw_kmac_smoketest	2.504m	3.042ms	1	1	100.00
		chip_sw_otbn_smoketest	13.282m	8.305ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.189m	5.488ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.322m	5.481ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.871m	2.851ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.018m	2.985ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.817m	2.821ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.844m	2.840ms	1	1	100.00
		chip_sw_uart_smoketest	2.123m	2.967ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.855m	2.863ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.363m	4.370ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.954h	60.369ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.953m	14.947ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.158m	5.249ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	5.286m	4.372ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.647m	10.138ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.741h	53.228ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.844h	55.976ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	41.380s	2.419ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	41.380s	2.419ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	50.797m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.869m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.943m	4.494ms	1	1	100.00
		chip_csr_rw	2.393m	4.043ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	50.797m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.869m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.943m	4.494ms	1	1	100.00
		chip_csr_rw	2.393m	4.043ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	45.610s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.690s	51.903us	1	1	100.00
		xbar_smoke_large_delays	43.440s	7.416ms	1	1	100.00
		xbar_smoke_slow_rsp	37.350s	4.510ms	1	1	100.00
		xbar_random_zero_delays	28.060s	587.063us	1	1	100.00
		xbar_random_large_delays	5.334m	54.598ms	1	1	100.00
		xbar_random_slow_rsp	4.629m	33.551ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.930s	1.309ms	1	1	100.00
		xbar_error_and_unmapped_addr	25.540s	1.303ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	43.600s	2.371ms	1	1	100.00
		xbar_error_and_unmapped_addr	25.540s	1.303ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	50.650s	2.200ms	1	1	100.00
		xbar_access_same_device_slow_rsp	9.034m	64.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	17.370s	1.063ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.085m	3.101ms	1	1	100.00
		xbar_stress_all_with_error	1.019m	3.101ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.178m	7.159ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.207m	7.159ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.953m	14.947ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	32.374m	25.756ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.535m	14.928ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.834m	11.227ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	38.352m	15.586ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.742m	15.586ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	37.658m	15.586ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	36.628m	14.887ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.040s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	24.730s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	24.950s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.090s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	24.870s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.220s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	25.890s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	25.560s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.600s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.440s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.980s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.320s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	26.410s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	26.310s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.980s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.060s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.700s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	26.000s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.360s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.450s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.080s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	26.340s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.770s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	26.290s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	25.390s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.938m	11.235ms	1	1	100.00
		rom_e2e_asm_init_dev	36.400m	15.603ms	1	1	100.00
		rom_e2e_asm_init_prod	37.690m	15.602ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.245m	15.603ms	1	1	100.00
		rom_e2e_asm_init_rma	35.511m	14.903ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.295m	15.067ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.179m	15.031ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.348m	15.031ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	37.180m	15.873ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.294m	18.575ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.294m	18.575ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.102m	2.956ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.022m	2.974ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.994m	2.851ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.034m	2.865ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.131m	9.553ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.172m	2.965ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.037m	4.782ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.508m	5.493ms	1	1	100.00
		chip_plic_all_irqs_10	3.446m	3.655ms	1	1	100.00
		chip_plic_all_irqs_20	5.180m	4.266ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.343m	3.262ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.292m	11.255ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.627m	4.866ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.750m	2.815ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.127m	11.333ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.547m	7.935ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.262m	7.698ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	10.359m	7.962ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.952h	255.002ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.077m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.189m	5.488ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.077m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.471m	7.874ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.471m	7.874ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.615m	6.728ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.534m	4.843ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.683m	6.001ms	1	1	100.00
		chip_sw_aes_idle	2.034m	2.865ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.125m	2.997ms	1	1	100.00
		chip_sw_kmac_idle	1.902m	2.847ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.258m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.332m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.176m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.216m	4.044ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.278m	9.294ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.089m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.912m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.217m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.017m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.074m	4.039ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.049m	4.655ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.856m	7.273ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.864m	5.739ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.217m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.017m	4.655ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.700m	4.100ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	7.941m	5.930ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	49.951m	18.978ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.022m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.588m	6.144ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.191m	2.973ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.616m	9.442ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.197m	3.083ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.205m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.768m	2.823ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.582m	2.830ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.718m	4.654ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.393m	7.273ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	46.254m	25.284ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.954m	3.047ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.073m	3.046ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.665m	9.556ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.356m	3.202ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.312m	4.556ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.408m	18.498ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.516h	68.236ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.856m	7.273ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.757m	4.612ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.187m	3.423ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.547m	7.935ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.125m	6.634ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.072m	2.881ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.733m	5.687ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.942m	2.871ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	41.406m	17.562ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.887m	2.847ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.902m	6.083ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.887m	2.847ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.125m	6.634ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.910m	2.842ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	14.787m	17.557ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.303m	5.584ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	7.941m	5.930ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.196m	3.956ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.700m	4.100ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	46.556m	43.040ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	14.787m	17.557ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.767m	3.444ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.245m	9.416ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.616m	4.437ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	46.556m	43.040ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.616m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.616m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.616m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.616m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.696m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.044m	5.134ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.045m	4.946ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.045m	4.946ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.154m	2.955ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.191m	2.973ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.125m	2.997ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.542m	3.103ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	10.049m	6.290ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.975m	5.359ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.210m	5.360ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.798m	5.359ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.862m	4.081ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.245m	9.416ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.616m	9.442ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	17.691m	9.471ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.131m	9.553ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.090m	14.244ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.932m	2.874ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.446m	3.052ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.197m	3.083ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.245m	9.416ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.851m	2.833ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	13.736m	8.266ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.902m	2.847ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.037m	4.782ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.441m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.849m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.502m	2.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.053m	2.880ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.573m	9.416ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.616m	4.437ms	1	1	100.00
		chip_sw_flash_rma_unlocked	46.556m	43.040ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.743m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.053m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.644m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.975m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.245m	9.416ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.705m	8.840ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.403m	7.136ms	1	1	100.00
		chip_prim_tl_access	1.696m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.864m	5.739ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.089m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.912m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.217m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.017m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.074m	4.039ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.049m	4.655ms	1	1	100.00
		chip_tap_straps_dev	1.441m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.849m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.502m	2.919ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.871m	10.388ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.056m	3.459ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.283m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.260m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.284m	3.372ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	16.563m	23.471ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.871m	10.388ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	52.498m	47.201ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	51.529m	47.201ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.516m	8.116ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	54.493m	45.726ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	16.563m	23.471ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	58.170s	2.488ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.050m	2.532ms	1	1	100.00
		rom_volatile_raw_unlock	1.046m	2.532ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	48.083m	17.348ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	49.951m	18.978ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.683m	6.001ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.683m	6.001ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.683m	6.001ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	3.796m	3.638ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	14.787m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.796m	3.638ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.245m	9.416ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.348m	4.352ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.938m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	14.787m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	3.796m	3.638ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.245m	9.416ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.348m	4.352ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.938m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.119m	4.519ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.053m	2.880ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.743m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.053m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.644m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.975m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.910m	5.714ms	1	1	100.00
		chip_prim_tl_access	1.696m	4.853ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.696m	4.853ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.003m	8.584ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.817m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.736m	23.874ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.309m	7.391ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	4.908m	7.690ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.674m	5.880ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.028m	21.458ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.782m	13.292ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.471m	7.874ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.412m	10.196ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.393m	4.448ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.817m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.201m	4.037ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	24.576m	29.986ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.791m	6.182ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.575m	4.818ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.085m	20.517ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.926m	6.806ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.639m	9.745ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.757m	22.554ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.155m	3.089ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.705m	8.840ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.705m	8.840ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.639m	9.745ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.085m	20.517ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.393m	4.448ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.189m	5.488ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.112m	3.958ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.337m	4.042ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.214m	3.947ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.292m	11.255ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.863m	2.872ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.262m	7.698ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.600m	4.812ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.529m	4.828ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.188m	3.003ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.938m	2.899ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.337m	4.042ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.337m	4.042ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.840m	9.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	12.667m	13.888ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.112m	3.958ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.851m	4.259ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.468m	5.726ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.849m	5.475ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.871m	10.388ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.508m	5.493ms	1	1	100.00
		chip_plic_all_irqs_10	3.446m	3.655ms	1	1	100.00
		chip_plic_all_irqs_20	5.180m	4.266ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.929m	2.863ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.160m	2.985ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.953m	14.947ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.571m	6.782ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.727m	3.148ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.606m	3.348ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.417m	3.019ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.348m	4.352ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.205m	4.391ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	4.853m	7.068ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.030m	7.152ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.403m	7.136ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.892m	5.209ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.926m	6.806ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.102m	22.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.967m	2.900ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.857m	3.615ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.371m	4.570ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.102m	22.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.102m	22.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.047m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.047m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.667m	5.614ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.294m	18.575ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.051m	2.855ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.945m	2.886ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.684m	3.645ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.305m	3.878ms	0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	14.606m	8.155ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.234h	31.580ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	25.036m	12.129ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.033m	2.913ms	1	1	100.00
V2		TOTAL			238	275	86.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.307m	2.946ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.957m	2.814ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.424h	71.627ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.566m	5.648ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.470m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.898m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.826m	11.323ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.603m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.612m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.657m	4.125ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.007s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	6.608m	5.154ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	3.852m	2.673ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	8.000m	4.389ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.246m	8.141ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.002m	2.215ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.090m	5.160ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	57.100s	2.427ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.772m	4.949ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.516m	5.531ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.713m	4.408ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.639m	9.745ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.470m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.898m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.826m	11.323ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.019s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.185m	4.945ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.384h	38.358ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.384h	38.358ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.222m	3.466ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.907m	4.272ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	40.710m	18.949ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.294m	3.011ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.836m	4.945ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.904m	2.864ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.414m	3.110ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.005m	3.828ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.009s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.527m	3.069ms	1	1	100.00
		TOTAL			280	325	86.15

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1
Line 495, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1
Line 500, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1
Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1
Line 487, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1
Line 504, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1
Line 487, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1
Line 487, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1
Line 487, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1
Line 487, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1
Line 490, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat" has 3 failures:
- Test chip_sw_uart_rand_baudrate has 1 failures.
  - 0.chip_sw_uart_rand_baudrate.1
    Line 403, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_rand_baudrate/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kUartBaudrate.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 3 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.097s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rv_dm_access_after_escalation_reset has 1 failures.

0.chip_sw_rv_dm_access_after_escalation_reset.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_escalation_reset/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:alert_handler_escalation_test_sim_dv': target 'alert_handler_escalation_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 0.127s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.122s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1
    Line 462, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1
    Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1
    Line 514, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1
    Line 510, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1
    Line 506, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1
    Line 532, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1
    Line 494, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_pwm_pulses_vseq.sv:55) virtual_sequencer [chip_sw_pwm_pulses_vseq] PWMCH* : lowpower counter is zero has 1 failures:
- Test chip_sw_sleep_pwm_pulses has 1 failures.
  - 0.chip_sw_sleep_pwm_pulses.1
    Line 477, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pwm_pulses/latest/run.log
```
  UVM_ERROR @ 8692.651924 us: (chip_sw_pwm_pulses_vseq.sv:55) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_pwm_pulses_vseq] PWMCH0 : lowpower counter is zero
  UVM_INFO @ 8692.651924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_usbdev_setuprx has 1 failures.
  - 0.chip_sw_usbdev_setuprx.1
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_usbdev_setuprx/latest/run.log
```
  UVM_ERROR @ 3878.269500 us: (sw_logger_if.sv:526) [usbdev_setuprx_test_sim_dv(sw/device/tests/usbdev_setuprx_test.c:208)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 3878.269500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 418, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3147.799500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3147.799500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98461) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4042.081836 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98461) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4042.081836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.1
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11579.002460 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11579.002460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1
    Line 410, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2965.019500 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 2965.019500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2815.359500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2815.359500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:579) [chip_sw_entropy_src_fuse_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert otp_ctrl_fatal_check_error fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.1
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2880.645347 us: (cip_base_vseq.sv:579) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert otp_ctrl_fatal_check_error fired unexpectedly!
  UVM_INFO @ 2880.645347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2419.289116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h106e8  a_data: 'h65c994b0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18abe  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2419.289116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.1
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2813.904500 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2813.904500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:104) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.1
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 4371.819500 us: (chip_sw_power_idle_load_vseq.sv:104) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 4371.819500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:127) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : no toggling signal has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1
    Line 439, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 10137.742420 us: (chip_sw_power_sleep_load_vseq.sv:127) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH0 : no toggling signal
  UVM_INFO @ 10137.742420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.1
    Line 431, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19266.254833 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19266.254833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1
    Line 452, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1
    Line 465, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1
Line 237, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2420.279116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: 'h104fc  a_data: 'hb08d55f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a9be  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2420.279116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---