ADC_CTRL Simulation Results

Tuesday March 25 2025 20:25:42 UTC

GitHub Revision: 138e258a73

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.750s	5.900ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.830s	983.793us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.720s	574.623us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	16.020s	26.650ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.240s	929.376us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.790s	602.040us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.720s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.240s	929.376us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	2.092m	326.507ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	2.075m	330.444ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.127m	324.779ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.075m	320.179ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	2.188m	343.342ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.496m	390.507ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	2.206m	339.714ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.630s	1.758ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.300s	4.575ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	12.850s	30.838ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	34.900s	78.778ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.661m	407.443ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.520s	545.456us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.520s	539.539us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.380s	799.250us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.380s	799.250us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.830s	983.793us	1	1	100.00
		adc_ctrl_csr_rw	1.720s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.240s	929.376us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.500s	1.894ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.830s	983.793us	1	1	100.00
		adc_ctrl_csr_rw	1.720s	574.623us	1	1	100.00
		adc_ctrl_csr_aliasing	2.240s	929.376us	1	1	100.00
		adc_ctrl_same_csr_outstanding	2.500s	1.894ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	3.180s	4.428ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.720s	4.548ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.720s	4.548ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.350s	13.351ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.1
      Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 1758090787 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 1758090787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---