CHIP Simulation Results

Thursday March 27 2025 20:22:02 UTC

GitHub Revision: `6619597f31`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.819m	2.819ms	1	1	100.00
		chip_sw_example_rom	1.107m	2.524ms	1	1	100.00
		chip_sw_example_manufacturer	1.828m	2.819ms	1	1	100.00
		chip_sw_example_concurrency	1.948m	2.874ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	1.852m	4.494ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.417m	4.043ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	7.825m	8.463ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	51.894m	31.903ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	43.770s	2.420ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	51.894m	31.903ms	1	1	100.00
		chip_csr_rw	2.417m	4.043ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.870s	185.153us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.862m	4.214ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.862m	4.214ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.862m	4.214ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	4.697m	4.274ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	4.697m	4.274ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	4.940m	4.273ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.768m	4.274ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.726m	4.274ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	4.109m	3.821ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	4.716m	3.866ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.452m	3.990ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	1.921m	4.384ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	1.921m	4.384ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.370m	3.138ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.378m	5.503ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.389m	3.737ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.447m	2.919ms	1	1	100.00
		chip_tap_straps_testunlock0	3.900m	5.475ms	1	1	100.00
		chip_tap_straps_rma	3.846m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.514m	2.919ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.189m	2.953ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	10.729m	8.698ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.788m	5.209ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.788m	5.209ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	7.639m	7.273ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	28.022m	19.266ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.648m	4.100ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	7.413m	5.930ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	49.034m	18.978ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.139m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.285m	6.144ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.036m	2.973ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.356m	9.442ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.319m	3.083ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.542m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.832m	2.823ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.531m	3.122ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.565m	6.596ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.296m	5.231ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.000m	2.893ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.296m	5.231ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.975m	2.820ms	1	1	100.00
		chip_sw_aes_smoketest	2.210m	2.956ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.243m	3.088ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.832m	2.839ms	1	1	100.00
		chip_sw_csrng_smoketest	1.903m	2.844ms	1	1	100.00
		chip_sw_entropy_src_smoketest	3.690m	3.598ms	1	1	100.00
		chip_sw_gpio_smoketest	2.348m	3.074ms	1	1	100.00
		chip_sw_hmac_smoketest	2.534m	3.200ms	1	1	100.00
		chip_sw_kmac_smoketest	2.401m	3.042ms	1	1	100.00
		chip_sw_otbn_smoketest	12.698m	8.305ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.256m	5.488ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.445m	5.481ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.991m	2.851ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.048m	2.985ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.788m	2.821ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.885m	2.840ms	1	1	100.00
		chip_sw_uart_smoketest	1.978m	2.967ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.929m	2.863ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.106m	4.370ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.909h	60.476ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	37.864m	14.947ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.088m	5.249ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.758m	3.304ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.645m	3.299ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.713h	53.228ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.853h	55.976ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	39.150s	2.419ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	39.150s	2.419ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	51.894m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.500m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.852m	4.494ms	1	1	100.00
		chip_csr_rw	2.417m	4.043ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	51.894m	31.903ms	1	1	100.00
		chip_same_csr_outstanding	13.500m	15.238ms	1	1	100.00
		chip_csr_hw_reset	1.852m	4.494ms	1	1	100.00
		chip_csr_rw	2.417m	4.043ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	47.310s	2.371ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.440s	51.903us	1	1	100.00
		xbar_smoke_large_delays	43.260s	7.416ms	1	1	100.00
		xbar_smoke_slow_rsp	37.240s	4.510ms	1	1	100.00
		xbar_random_zero_delays	30.510s	587.063us	1	1	100.00
		xbar_random_large_delays	5.253m	54.598ms	1	1	100.00
		xbar_random_slow_rsp	4.602m	33.551ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	31.800s	1.309ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.790s	1.303ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	43.960s	2.371ms	1	1	100.00
		xbar_error_and_unmapped_addr	26.790s	1.303ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	52.980s	2.200ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.981m	64.252ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	19.040s	1.063ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.087m	3.101ms	1	1	100.00
		xbar_stress_all_with_error	1.010m	3.101ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	5.317m	7.159ms	1	1	100.00
		xbar_stress_all_with_reset_error	4.126m	7.159ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	37.864m	14.947ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	32.721m	25.756ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.889m	14.928ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.559m	11.227ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.612m	15.586ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.136m	15.586ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.706m	15.586ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	36.343m	14.887ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.040s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	25.050s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	25.440s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.040s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	24.600s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	25.030s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	25.010s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	27.110s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.730s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	26.000s	10.340us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	25.440s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	25.430s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	25.590s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.790s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.910s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.790s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	25.900s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.750s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	25.360s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.550s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	26.260s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	25.390s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	25.940s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.240s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	25.590s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.003m	11.235ms	1	1	100.00
		rom_e2e_asm_init_dev	35.815m	15.603ms	1	1	100.00
		rom_e2e_asm_init_prod	36.381m	15.602ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.811m	15.603ms	1	1	100.00
		rom_e2e_asm_init_rma	35.674m	14.903ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.518m	15.067ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.609m	15.031ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	33.806m	15.031ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	35.509m	15.873ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.586m	18.575ms	1	1	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.586m	18.575ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.087m	2.956ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.139m	2.974ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.913m	2.851ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.987m	2.865ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	17.041m	9.553ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.027m	2.965ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.128m	4.782ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.815m	5.493ms	1	1	100.00
		chip_plic_all_irqs_10	3.502m	3.655ms	1	1	100.00
		chip_plic_all_irqs_20	4.804m	4.266ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.433m	3.361ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	13.042m	10.635ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.240m	4.245ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.888m	2.815ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.031m	11.333ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.572m	7.937ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.097m	7.696ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	10.756m	7.962ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.933h	255.002ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.291m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.256m	5.488ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.291m	3.940ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.487m	7.874ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.487m	7.874ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.565m	6.728ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.350m	4.843ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.486m	6.001ms	1	1	100.00
		chip_sw_aes_idle	1.987m	2.865ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.349m	2.997ms	1	1	100.00
		chip_sw_kmac_idle	2.013m	2.847ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.217m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.421m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.306m	4.044ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.268m	4.044ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.518m	9.294ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.407m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.942m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.148m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.939m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.142m	4.039ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.950m	4.655ms	1	1	100.00
		chip_sw_ast_clk_outputs	7.639m	7.273ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.223m	5.739ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.148m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.939m	4.655ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.648m	4.100ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	7.413m	5.930ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	49.034m	18.978ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.139m	2.974ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.285m	6.144ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.036m	2.973ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.356m	9.442ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.319m	3.083ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.542m	4.391ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.832m	2.823ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.811m	2.830ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.827m	4.654ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	8.684m	7.273ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	45.979m	25.284ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.043m	3.047ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.111m	3.046ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	11.759m	9.556ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.304m	3.202ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.220m	4.556ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.323m	18.498ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.518h	68.236ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	7.639m	7.273ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.643m	4.612ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.047m	3.423ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	13.572m	7.937ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.507m	6.634ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.008m	2.881ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	4.782m	5.687ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.945m	2.871ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	43.196m	17.562ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.956m	2.847ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.603m	6.083ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.956m	2.847ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.507m	6.634ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.948m	2.842ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	14.885m	17.557ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.075m	5.584ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	7.413m	5.930ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.817m	3.956ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.648m	4.100ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	46.919m	43.040ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	14.885m	17.557ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.655m	3.444ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.715m	9.416ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.824m	4.437ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	46.919m	43.040ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.824m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.824m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.824m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.824m	4.437ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.667m	4.853ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.492m	5.134ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.386m	4.946ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.386m	4.946ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.246m	2.955ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.036m	2.973ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.349m	2.997ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.645m	3.103ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	10.165m	6.290ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.654m	5.359ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.960m	5.360ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.609m	5.359ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.846m	4.081ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.715m	9.416ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	14.356m	9.442ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	16.282m	9.471ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	17.041m	9.553ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.838m	14.244ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.935m	2.874ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.344m	3.052ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.319m	3.083ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.715m	9.416ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.864m	2.833ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.626m	8.266ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.013m	2.847ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.128m	4.782ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.447m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.846m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.514m	2.919ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.909m	2.880ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.431m	9.416ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.824m	4.437ms	1	1	100.00
		chip_sw_flash_rma_unlocked	46.919m	43.040ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.853m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.095m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.772m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.225m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.715m	9.416ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.622m	8.840ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.162m	7.136ms	1	1	100.00
		chip_prim_tl_access	1.667m	4.853ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.223m	5.739ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.407m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.942m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.148m	4.038ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.939m	4.655ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.142m	4.039ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.950m	4.655ms	1	1	100.00
		chip_tap_straps_dev	1.447m	2.919ms	1	1	100.00
		chip_tap_straps_rma	3.846m	5.475ms	1	1	100.00
		chip_tap_straps_prod	1.514m	2.919ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.642m	10.388ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.174m	3.459ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.218m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.267m	3.372ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.255m	3.372ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	16.957m	23.471ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.642m	10.388ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	53.276m	47.201ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	52.496m	47.201ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.710m	8.116ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	51.160m	45.726ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	16.957m	23.471ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	57.850s	2.488ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.056m	2.532ms	1	1	100.00
		rom_volatile_raw_unlock	1.032m	2.532ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	48.789m	17.348ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	49.034m	18.978ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.486m	6.001ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.486m	6.001ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.486m	6.001ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.139m	3.638ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	14.885m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.139m	3.638ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.715m	9.416ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.581m	4.352ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.043m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	14.885m	17.557ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.139m	3.638ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.715m	9.416ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.581m	4.352ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.043m	2.899ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.898m	4.519ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.909m	2.880ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	2.853m	3.266ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.095m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.772m	6.033ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.225m	6.038ms	1	1	100.00
		chip_sw_lc_ctrl_transition	3.948m	5.714ms	1	1	100.00
		chip_prim_tl_access	1.667m	4.853ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.667m	4.853ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	13.878m	8.584ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	3.620m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	13.579m	23.874ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.276m	7.391ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.238m	7.690ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.999m	5.880ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.672m	21.458ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.538m	13.292ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.487m	7.874ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.704m	10.196ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.275m	4.448ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	3.620m	7.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.232m	4.037ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	26.027m	29.986ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.523m	6.182ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.625m	4.818ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.802m	20.517ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.747m	6.806ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.735m	9.745ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	18.707m	22.554ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.186m	3.089ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.622m	8.840ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.622m	8.840ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.735m	9.745ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.802m	20.517ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.275m	4.448ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.256m	5.488ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.105m	3.958ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.333m	4.042ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.166m	3.947ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	13.042m	10.635ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.986m	2.872ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.097m	7.696ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.414m	4.812ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.526m	4.828ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.294m	3.003ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.043m	2.899ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.333m	4.042ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.333m	4.042ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	7.968m	9.373ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.923m	13.888ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.105m	3.958ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.937m	4.259ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.665m	5.726ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.846m	5.475ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.642m	10.388ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.815m	5.493ms	1	1	100.00
		chip_plic_all_irqs_10	3.502m	3.655ms	1	1	100.00
		chip_plic_all_irqs_20	4.804m	4.266ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.056m	2.863ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.070m	2.985ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	37.864m	14.947ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.924m	6.782ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.562m	3.148ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.732m	3.348ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.362m	3.019ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.581m	4.352ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.542m	4.391ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.048m	7.068ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.122m	7.153ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.162m	7.136ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.788m	5.209ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.747m	6.806ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	13.354m	22.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.005m	2.900ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.900m	3.615ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.506m	4.570ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	13.354m	22.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	13.354m	22.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	10.117m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	10.117m	11.579ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.676m	5.614ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	4.586m	18.575ms	1	1	100.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.921m	2.855ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.018m	2.886ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.079m	3.645ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.778m	3.935ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	13.876m	8.155ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.189h	31.580ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	25.625m	12.129ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.008m	2.913ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.387m	2.946ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.918m	2.814ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.389h	71.627ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.396m	5.648ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.938m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.664m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.960m	11.323ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.502m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.637m	4.125ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.658m	4.125ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.024s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.718m	5.154ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.104m	2.673ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.216m	4.389ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	14.948m	8.141ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	2.849m	2.215ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.202m	5.160ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	54.890s	2.427ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.416m	4.949ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.449m	5.531ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.579m	4.408ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.735m	9.745ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.938m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.664m	11.323ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.960m	11.323ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.352m	4.819ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.699m	4.945ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.326h	38.358ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.326h	38.358ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.371m	3.466ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	4.697m	4.274ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	41.838m	18.949ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.072m	3.011ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	4.853m	4.945ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.973m	2.864ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.494m	3.110ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.081m	3.828ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.009s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.480m	3.069ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:

Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1
Line 516, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1
Line 518, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1
Line 491, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1
Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1
Line 514, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:

Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1
Line 506, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1
Line 505, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1
Line 494, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1
Line 502, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1
Line 521, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log

  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1
    Line 483, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1
    Line 501, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1
    Line 503, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.473s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.1
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.136s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1
    Line 535, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1
    Line 477, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1
    Line 547, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1
    Line 482, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3147.799500 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3147.799500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98461) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4042.081836 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98461) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4042.081836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.1
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11579.002460 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:197)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11579.002460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2965.019500 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 2965.019500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1
    Line 407, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2815.359500 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2815.359500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:579) [chip_sw_entropy_src_fuse_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert otp_ctrl_fatal_check_error fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.1
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2880.645347 us: (cip_base_vseq.sv:579) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert otp_ctrl_fatal_check_error fired unexpectedly!
  UVM_INFO @ 2880.645347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2419.289116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h106e8  a_data: 'h65c994b0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18abe  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2419.289116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.1
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 2813.904500 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2813.904500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.1
    Line 413, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3304.126000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3304.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3299.126000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3299.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.1
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19266.254833 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:128)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19266.254833 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1
    Line 457, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1
    Line 471, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.1
Line 237, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2420.279116 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32041) { a_addr: 'h104fc  a_data: 'hb08d55f2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1a9be  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2420.279116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---