HMAC Simulation Results

Monday March 31 2025 20:14:32 UTC

GitHub Revision: 1eaf8e5dc0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.080s 1.191ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.590s 76.786us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.650s 64.161us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.660s 1.919ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.150s 729.208us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.780s 59.827us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.650s 64.161us 1 1 100.00
hmac_csr_aliasing 3.150s 729.208us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 34.300s 13.978ms 1 1 100.00
V2 back_pressure hmac_back_pressure 9.060s 945.959us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.310s 748.791us 1 1 100.00
hmac_test_sha384_vectors 17.980s 914.876us 1 1 100.00
hmac_test_sha512_vectors 18.710s 914.876us 1 1 100.00
hmac_test_hmac256_vectors 6.070s 781.500us 1 1 100.00
hmac_test_hmac384_vectors 7.940s 1.117ms 1 1 100.00
hmac_test_hmac512_vectors 7.810s 968.751us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.800s 7.347ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.921m 6.680ms 1 1 100.00
V2 error hmac_error 40.640s 17.172ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 18.770s 8.220ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.080s 1.191ms 1 1 100.00
hmac_long_msg 34.300s 13.978ms 1 1 100.00
hmac_back_pressure 9.060s 945.959us 1 1 100.00
hmac_datapath_stress 2.921m 6.680ms 1 1 100.00
hmac_burst_wr 17.800s 7.347ms 1 1 100.00
hmac_stress_all 54.380s 22.732ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.080s 1.191ms 1 1 100.00
hmac_long_msg 34.300s 13.978ms 1 1 100.00
hmac_back_pressure 9.060s 945.959us 1 1 100.00
hmac_datapath_stress 2.921m 6.680ms 1 1 100.00
hmac_wipe_secret 18.770s 8.220ms 1 1 100.00
hmac_test_sha256_vectors 8.310s 748.791us 1 1 100.00
hmac_test_sha384_vectors 17.980s 914.876us 1 1 100.00
hmac_test_sha512_vectors 18.710s 914.876us 1 1 100.00
hmac_test_hmac256_vectors 6.070s 781.500us 1 1 100.00
hmac_test_hmac384_vectors 7.940s 1.117ms 1 1 100.00
hmac_test_hmac512_vectors 7.810s 968.751us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.080s 1.191ms 1 1 100.00
hmac_long_msg 34.300s 13.978ms 1 1 100.00
hmac_back_pressure 9.060s 945.959us 1 1 100.00
hmac_datapath_stress 2.921m 6.680ms 1 1 100.00
hmac_burst_wr 17.800s 7.347ms 1 1 100.00
hmac_error 40.640s 17.172ms 1 1 100.00
hmac_wipe_secret 18.770s 8.220ms 1 1 100.00
hmac_test_sha256_vectors 8.310s 748.791us 1 1 100.00
hmac_test_sha384_vectors 17.980s 914.876us 1 1 100.00
hmac_test_sha512_vectors 18.710s 914.876us 1 1 100.00
hmac_test_hmac256_vectors 6.070s 781.500us 1 1 100.00
hmac_test_hmac384_vectors 7.940s 1.117ms 1 1 100.00
hmac_test_hmac512_vectors 7.810s 968.751us 1 1 100.00
hmac_stress_all 54.380s 22.732ms 1 1 100.00
V2 stress_all hmac_stress_all 54.380s 22.732ms 1 1 100.00
V2 alert_test hmac_alert_test 1.340s 40.910us 1 1 100.00
V2 intr_test hmac_intr_test 1.410s 39.577us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.260s 363.496us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.260s 363.496us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.590s 76.786us 1 1 100.00
hmac_csr_rw 1.650s 64.161us 1 1 100.00
hmac_csr_aliasing 3.150s 729.208us 1 1 100.00
hmac_same_csr_outstanding 1.960s 205.870us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.590s 76.786us 1 1 100.00
hmac_csr_rw 1.650s 64.161us 1 1 100.00
hmac_csr_aliasing 3.150s 729.208us 1 1 100.00
hmac_same_csr_outstanding 1.960s 205.870us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.550s 155.911us 1 1 100.00
hmac_tl_intg_err 2.110s 367.496us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.110s 367.496us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.080s 1.191ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.650s 786.500us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 21.440s 7.676ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.630s 50.223us 1 1 100.00
TOTAL 28 28 100.00